test.vhd

多路并行扰码

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test is
port( reset, clk : in std_logic;
	 datin : in std_logic_vector( 9 downto 0 );
	 datout : out std_logic_vector( 9 downto 0 ) );
end test;

architecture test of test is
    -- Component declarations
	component pscrambler
		port(
			reset 	: in std_logic;
			en	 	: in std_logic;
			clk		: in std_logic;
			clken	: in std_logic;
			datin	: in std_logic_vector( 1 to 10 );
			datout	: out std_logic_vector( 1 to 10 )
			);
    end component;

	component pdescrambler
		port(
			reset 	: in std_logic;
			en	 	: in std_logic;
			clk		: in std_logic;
			clken	: in std_logic;
			datin	: in std_logic_vector( 1 to 10 );
			datout	: out std_logic_vector( 1 to 10 )
			);
    end component;

signal scrambled : std_logic_vector( 9 downto 0 );
signal en, clken : std_logic;
begin

en <= '1';
clken <= '1';

u_s : pscrambler
port map ( reset => reset, en => en, clken => clken, clk => clk, datin => datin, datout => scrambled );

u_d : pdescrambler
port map ( reset => reset, en => en, clken => clken, clk => clk, datin => scrambled, datout => datout );

end test;