mul2.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    15:40:44 04/07/08
-- Design Name:    
-- Module Name:    mul2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul2 is
	port(	
--			clk:std_logic;
--			en_all:std_logic;
--			en_con:std_logic;
			mul2_in:in std_logic_vector(12 downto 0);	  --msb_lsb
			mul2_out:out std_logic_vector(12 downto 0)
			);
end mul2;

architecture Behavioral of mul2 is

begin
--process(clk)
--begin
--if(en_all='1' and en_con='0')then
mul2_out(0)<=mul2_in(11);
mul2_out(1)<=mul2_in(11) xor mul2_in(12);
mul2_out(2)<=mul2_in(12) xor mul2_in(0);
mul2_out(3)<=mul2_in(1) xor mul2_in(11);
mul2_out(4)<=mul2_in(2) xor mul2_in(12) xor mul2_in(11);
mul2_out(5)<=mul2_in(3) xor mul2_in(12);
mul2_out(6)<=mul2_in(4);
mul2_out(7)<=mul2_in(5);
mul2_out(8)<=mul2_in(6);
mul2_out(9)<=mul2_in(7);
mul2_out(10)<=mul2_in(8);
mul2_out(11)<=mul2_in(9);
mul2_out(12)<=mul2_in(10);
--end if;
--end process;
end Behavioral;