qpsk.vhd

qpsk vhdl code ue to impelemented on fpga kits

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity qpsk is
	port(
		ClkxCI		: in std_logic;
		ResetxRBI	: in std_logic;
				
		
		DataInxDI		: in std_logic_vector(23 downto 0);
		DataInReqxSI	: in std_logic;
		DataInAckxSO	: out std_logic;
		
		DataOutxDO		: out std_logic_vector(23 downto 0);
		DataOutReqxSO	: out std_logic;
		DataOutAckxSI	: in std_logic
		
		);
end qpsk;

architecture rtl of qpsk is

component LUT_Odd
	generic (
		width : integer;
		aw	  : integer);
		
	port (

	AddrxDIO : in std_logic_vector(aw-1 downto 0);
	DataxDOO : out std_logic_vector(width-1 downto 0));
end component;

component LUT_Even
	generic (
		width : integer;
		aw	  : integer);
		
	port (

	AddrxDIE : in std_logic_vector(aw-1 downto 0);
	DataxDOE : out std_logic_vector(width-1 downto 0));
end component;

component RAM_Odd
	generic (
		width : integer;
		aw	  : integer);
		
	port (

	AddrxDIO : in std_logic_vector(aw-1 downto 0);
	WExSIO	 : in std_logic;
	EnxSIO	 : in std_logic;
	WClkxCI	 : in std_logic;
	DinxDIO	 : in std_logic_vector(width-1 downto 0);
	DoutxDOO : out std_logic_vector(width-1 downto 0));
end component;

component RAM_Even
	generic (
		width : integer;
		aw	  : integer);
		
	port (

	AddrxDIE : in std_logic_vector(aw-1 downto 0);
	WExSIE	 : in std_logic;
	EnxSIE	 : in std_logic;
	WClkxCI	 : in std_logic;
	DinxDIE	 : in std_logic_vector(width-1 downto 0);
	DoutxDOE : out std_logic_vector(width-1 downto 0));
end component;

signal InRegEnxS				: std_logic;
signal InRegxDP, InRegxDN		: std_logic_vector(23 downto 0);


--counters
signal OffsetDecxSO				: std_logic;
signal OffsetxDPO, OffsetxDNO	: unsigned(11 downto 0);
signal CounterIncxSO			: std_logic;
signal CounterxDPO, CounterxDNO	: unsigned(11 downto 0);
signal OffsetDecxSE				: std_logic;
signal OffsetxDPE, OffsetxDNE	: unsigned(11 downto 0);
signal CounterIncxSE			: std_logic;
signal CounterxDPE, CounterxDNE	: unsigned(11 downto 0);
signal RamAddrxDO				: std_logic_vector(11 downto 0);
signal LutAddrxDO				: std_logic_vector(11 downto 0);
signal RamAddrxDE				: std_logic_vector(11 downto 0);
signal LutAddrxDE				: std_logic_vector(11 downto 0);
signal RamWriteEnxSO			: std_logic;
signal RamWriteEnxSE			: std_logic;
signal RamWritexSE				: std_logic;
signal RamWritexSO				: std_logic;
signal CounterIncxS				: std_logic;
signal OffsetxDecxS				: std_logic;
signal Count, Count1			: unsigned(1 downto 0);
signal wala, wala1				: unsigned(11 downto 0);
signal Countdown				: std_logic;
signal Odd, Even				: std_logic;

--alu signals
signal SumxD					: signed(35 downto 0);
signal SumxO					: signed(35 downto 0);
signal SumxE					: signed(35 downto 0);
signal RamSignedxDO				: signed(23 downto 0);
signal RamSignedxDE				: signed(23 downto 0);
signal LutSignedxDO				: signed(11 downto 0);
signal LutSignedxDE				: signed(11 downto 0);
signal RamReadxDO				: std_logic_vector(23 downto 0);
signal RamReadxDE				: std_logic_vector(23 downto 0);
signal LutReadxDO				: std_logic_vector(11 downto 0);
signal LutReadxDE				: std_logic_vector(11 downto 0);
signal SumStdxD					: std_logic_vector(35 downto 0);

--out signal
signal OutRegENxS				: std_logic;
signal OutRegxDP, OutRegxDN		: std_logic_vector(23 downto 0);
signal DataOutReqxS				: std_logic;

--fsm
type state_type is (idle, new_data, run, data_out);
signal StatexDP, StatexDN : state_type;

begin

	InRegxDN <= DataInxDI;
	
p_inreg : process (ClkxCI, ResetxRBI)

		begin
			if ResetxRBI = '0' then
				InRegxDP <= (others => '0');
				
			elsif ClkxCI'event and ClkxCI = '1' then
				if InRegEnxS = '1' then
					InRegxDP <= InRegxDN;
				end if;
			end if;
		end process p_inreg;
		
p_select: process (Countdown, wala, wala1, Count, Count1, Odd, Even) 
		
		begin
		wala <= wala1;
		
				if Countdown <='1' then
					
					Count <= Count1;
					
						if Count <= "01" then
							Odd <= '1';
							Even <= '0';
							Count <= Count1 + "01";
						elsif Count = "10" then
							Even <= '1';
							Odd <= '0';
							Count <= Count1 - "01";
						
						end if;
					
					wala <= wala1 + "000000000001";
				end if;
			
		end process p_select;
		
p_dataOdd: process (OffsetxDPO, OffsetDecxSO, OffsetxDPE, OffsetDecxSE)

		begin
			OffsetxDNO <= OffsetxDPO;
			OffsetxDNE <= OffsetxDPE;
			if OffsetDecxSO = '1' then
				OffsetxDNO <= OffsetxDPO - "000000000001";
			elsif OffsetDecxSE = '1' then
				OffsetxDNE <= OffsetxDPE - "000000000001";
			end if;
		end process p_dataOdd;
		
p_lutOdd: process (CounterxDPO, CounterIncxSO, CounterxDPE, CounterIncxSE)

		begin 
			CounterxDNO <= CounterxDPO;
			CounterxDNE <= CounterxDPE;
			if CounterIncxSO = '1' then
				CounterxDNO <= CounterxDPO + "000000000001";
			elsif CounterIncxSE = '1' then
				CounterxDNE <= CounterxDPE + "000000000001";
			end if;
		end process p_lutOdd;

p_addclkOdd: process (ClkxCI, ResetxRBI)

		begin
			if ResetxRBI = '0' then
				CounterxDPO <= (others => '0');
				OffsetxDPO <= (others => '0');
				CounterxDPE <= (others => '0');
				OffsetxDPE <= (others => '0');

				
			elsif ClkxCI'event and ClkxCI = '1' then
				wala1 <= wala;
				CounterxDPO <= CounterxDNO;
				OffsetxDPO <= OffsetxDNO;
				CounterxDPE <= CounterxDNE;
				OffsetxDPE <= OffsetxDNE;
			end if;
		end process p_addclkOdd;

RamAddrxDO <= std_logic_vector(OffsetxDPO + CounterxDPO);
LutAddrxDO <= std_logic_vector(CounterxDPO);
RamAddrxDE <= std_logic_vector(OffsetxDPE + CounterxDPE);
LutAddrxDE <= std_logic_vector(CounterxDPE);

--alu

RamSignedxDO <= signed(RamReadxDO);
RamSignedxDE <= signed(RamReadxDE);
LutSignedxDO <= signed(LutReadxDO);
LutSignedxDE <= signed(LutReadxDE);

SumxO <= RamSignedxDO *  LutSignedxDO; 
SumxE <= RamSignedxDE *  LutSignedxDE; 

SumxD <= SumxO + SumxE;

SumStdxD <= std_logic_vector(SumxD);

OutRegxDN <= SumStdxD(35 downto 12);

p_outreg: process (ClkxCI, ResetxRBI)

			begin
				if ResetxRBI = '0' then
					OutRegxDP <= (others => '0');
				elsif ClkxCI'event and ClkxCI = '1' then
					if OutRegENxS = '1' then
						OutRegxDP <= OutRegxDN;
					end if;
				end if;
			end process p_outreg;
			
DataOutxDO <= OutRegxDP;

--fsm

p_fsm: process(StatexDP, DataInReqxSI, DataOutAckxSI, CounterxDPO)
			begin
			
			InRegEnxS		<= '0';
			OutRegEnxS		<= '0';
			OffsetDecxSO	<= '0';
			CounterIncxSO	<= '0';
			OffsetDecxSE	<= '0';
			CounterIncxSE	<= '0';
			RamWriteEnxSO	<= '0';
			RamWriteEnxSE	<= '0';
			DataInAckxSO	<= '0';
			DataOutReqxS	<= '0';
			Countdown		<= '0';
			
			StatexDN <= StatexDP;
			
			case StatexDP is
				when idle =>
					if DataInReqxSI = '1' then
						InRegEnxS <= '1';
						StatexDN <= new_data;
					end if;
					
				when new_data =>
		
						Countdown <= '1';
						RamWriteEnxSO <= '1';
						RamWriteEnxSE <= '1';
						DataInAckxSO <= '1';
						RamWritexSO <= Odd;
						RamWritexSE <= Even;
						
					if wala = "111111111111" then	
						StatexDN <= run;
					end if;
				when run =>
					CounterIncxS <= '1';
					if CounterxDPE = "111111111111" then
						OutRegEnxS <= '1';
						OffsetxDecxS <= '1';
						StatexDN <= data_out;
					end if;
					
				when data_out =>
					DataOutReqxSO <= '1';
					if DataOutAckxSI = '1' then
						StatexDN <= idle;
					end if;
				
				when others => null;
			end case;
			end process p_fsm;
			
p_clk: process(ClkxCI, ResetxRBI)
			begin
				if ResetxRBI = '0' then
					StatexDP <= idle;
				elsif ClkxCI'event and ClkxCI = '1' then
					StatexDP <= StatexDN;
				end if;
			end process p_clk;

i_LUT_Odd : LUT_Odd
			
			generic map (
				width => 12 ,
				aw	  => 12 )
				
			port map (
				AddrxDIO => LutAddrxDO,
				DataxDOO => LutReadxDO);

i_LUT_Even : LUT_Even
			
			generic map (
				width => 12,
				aw	  => 12)
				
			port map (
				AddrxDIE => LutAddrxDE,
				DataxDOE => LutReadxDE);

i_RAM_Odd : RAM_Odd

			generic map (
				width => 24,
				aw	  => 12)
				
			port map (
				AddrxDIO => RamAddrxDO,
				WExSIO	 => RamWriteEnxSO,
				EnxSIO	 => RamWritexSO,
				WClkxCI	 => ClkxCI,
				DinxDIO	 => InRegxDP,
				DoutxDOO => RamReadxDO);

i_RAM_Even : RAM_Even

			generic map (
				width => 24,
				aw	  => 12)
				
			port map (
				AddrxDIE => RamAddrxDE,
				WExSIE	 => RamWriteEnxSE,
				EnxSIE	 => RamWritexSE,
				WClkxCI	 => ClkxCI,
				DinxDIE	 => InRegxDP,
				DoutxDOE => RamReadxDE);
								
end rtl;