hdb3dec.vhd

HDB3编解码

--********************************************************************************--
--                                                                                --
--  HDB3 Decoder                                                                  --
--                                                                                --
--********************************************************************************--



library IEEE;
use IEEE.std_logic_1164.all;


entity hdb3dec is
	port
	(
		hdb3x : in std_logic ;
        	hdb3y : in std_logic ;
		clk : in std_logic ;
		reset : in std_logic ;
		nrz : out std_logic ;
        	clk2m :out std_logic;
		clk2mlocal: in std_logic;
		aisalm: out std_logic;
		losalm: out std_logic 
	);
begin
end hdb3dec;


architecture structure of hdb3dec is

	component cnt3
	port
		(
		clk : in std_logic ;
		dir,reset : in std_logic ;
        	q : out std_logic_vector(2 downto 0)
		) ;
	end component ;

	component clkregen
	port
        	(
        	sgnlx,sgnly : in std_logic ;
		reset : in std_logic;
        	clk : in std_logic ;
        	clk2m : out std_logic
    		) ;
	end component ;
    
	component decoder
	port
        	(
        	sgnl : in std_logic_vector (1 downto 0) ;
        	clk2m : in std_logic ;
		reset : in std_logic ;
        	data : out std_logic 
	        ) ;
	end component ;

	component aislosdc
	port
		(
		clk2mlocal: in std_logic;
		nrzin: in std_logic;
		hdb3xreb: in std_logic;
		hdb3yreb: in std_logic;
		aisalm: out std_logic;
		losalm: out std_logic
		) ;
	end component ; 

	signal tempx,tempy : std_logic_vector(2 downto 0) ;
	signal preclk2m : std_logic ;
	signal nrzdec : std_logic;
            
begin
	
	u1: cnt3
	        port map (clk=>clk, dir=>hdb3x, reset=>reset, q=>tempx) ;

	u2: cnt3
        	port map (clk=>clk, dir=>hdb3y, reset=>reset, q=>tempy) ;

	u3: clkregen
        	port map (sgnlx=>tempx(2), sgnly=>tempy(2), 
				reset=>reset, clk=>clk, clk2m=>preclk2m) ;

	u4: decoder
        	port map (sgnl(0)=>tempx(2), sgnl(1)=>tempy(2), clk2m=>preclk2m, reset=>reset, 
				data=>nrzdec) ;
	u5: aislosdc
		port map (clk2mlocal=>clk2mlocal, nrzin=>nrzdec, hdb3xreb=>tempx(2), hdb3yreb=>tempy(2), aisalm=>aisalm, losalm=>losalm) ;

	nrz<=nrzdec;
	clk2m<=preclk2m ;

end structure ;