代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/168634/5441344
vhd alub.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *
www.eeworm.com/read/167787/5452446
vhd atahost_dma_actrl.vhd
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller
www.eeworm.com/read/475739/6776814
bak clk_div.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(
clk50M: in std_logic;
clk1M,clk10K,clk100,clk500K: out std_logic
);
end clk_div;
arch
www.eeworm.com/read/475739/6776863
vhd clk_div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(
clk50M: in std_logic;
clk1M,clk10K,clk100,clk500K: out std_logic
);
end clk_div;
arch
www.eeworm.com/read/475579/6792012
vhd address.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity address is
port(
d:in std_logic;
fclk:in std_logic;
ass:out std_logic_vector(5 to 0)
www.eeworm.com/read/473074/6854803
vhd ps.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ps is
port(
k_data: in std_logic;
clk:in std_logic;
PA :buffer std_logic_vector(7 downto 0);
"data :out s
www.eeworm.com/read/472904/6859620
vhd sramcontroller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------
entity sramcontroller is
port
(clock:in std_logic;
datain:in std_logic_vecto
www.eeworm.com/read/472423/6868032
vhd tbjsa.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbjsa IS
PORT(
cp : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(4 downto 0));
END tbjsa;
ARCHITECTURE a OF tbjsa IS
COMPONENT JKFF
PORT (j
www.eeworm.com/read/423729/6890758
txt taxi.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity taxi is
port ( clk_256 :in std_logic;