tbjsa.vhd

几个VHDL实现的源程序及其代码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbjsa IS
	PORT(
		cp : IN	STD_LOGIC;
		q : OUT	STD_LOGIC_VECTOR(4 downto 0));
END tbjsa;
ARCHITECTURE a OF tbjsa IS
COMPONENT JKFF
   PORT (j   : IN STD_LOGIC;
      k   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
SIGNAL vcc : STD_LOGIC;
SIGNAL njk,nq : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
vcc <= '1';
njk(0) <= '1';
njk(1) <= nq(0);
njk(2) <= nq(0)and nq(1);
njk(3) <= nq(0)and nq(1)and nq(2);
njk(4) <= nq(0)and nq(1)and nq(2)and nq(3);
l1:
FOR i IN 4 downto 0 GENERATE
n_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i));
q(i) <= not nq(i);
END GENERATE;
END a;