alub.vhd

debussy中文使用手册

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-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
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-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
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-- *  to third parties, or used for any purpose other than that           *
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-- *  of Novas Software Inc.                                              *
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-- *  All rights reserved                                                 *
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-- ************************************************************************

--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: ALUB.v
--   description: this part performs the arithmetic and logic funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                CH: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ALUB is
  port (
    IR : in std_logic_vector(1 downto 0);
    IDB : in std_logic_vector(7 downto 0);
    PC : in std_logic_vector(7 downto 0);
    clock : in std_logic;
    reset : in std_logic;
    S1 : buffer std_logic;
    ALU : buffer std_logic_vector(7 downto 0);
    IXR : buffer std_logic_vector(7 downto 0);
    bus_mode : in std_logic_vector(2 downto 0);
    alu_mode : in std_logic_vector(2 downto 0);
    carry_mode : in std_logic;
    error_out : out std_logic;
    CH : in std_logic_vector(4 downto 0)
  );
end ALUB;

architecture RTL of ALUB is
signal X0  : std_logic_vector(7 downto 0);
signal IXR_tmp     : std_logic_vector(7 downto 0);
signal ACC_tmp     : std_logic_vector(7 downto 0);
signal ACC   : std_logic_vector(7 downto 0);
signal zero_flag     : std_logic;
signal carry_flag  : std_logic;
signal T2 : std_logic;
signal T3   : std_logic;
signal T4   : std_logic;
signal Y0       : std_logic_vector(7 downto 0);
signal Carry0  : std_logic;
signal Zero0    : std_logic;
signal n_din03  : std_logic_vector(7 downto 0);
signal n_eq0    : std_logic;
signal net_1  : std_logic;
signal net_2  : std_logic;
signal net_3  : std_logic;


component alulogic
port (a : in std_logic_vector(7 downto 0);
 b : in std_logic_vector(7 downto 0);
 cin : in std_logic;
 sel : in std_logic_vector(2 downto 0);
 o : buffer std_logic_vector(7 downto 0);
 carry : out std_logic;
 zero : out std_logic);
end component;


begin

 i_alulogic: alulogic
 	port map ( a => X0, b => Y0, cin => carry_mode, sel => alu_mode,
        o => ALU, carry => Carry0, zero => Zero0);

 process (IXR_tmp, PC, ACC_tmp, IDB, bus_mode)
 begin
        case bus_mode is
        when "000" => X0 <= IXR_tmp;
        when "001" => X0 <= ACC_tmp;
        when "010" => X0 <= PC;
        when "011" => X0 <= ACC_tmp;
        when "100" => X0 <= IDB;
        when "101" => X0 <= IDB;
        when "110" => X0 <= IDB;
        when "111" => X0 <= IDB;
        when others => X0 <= (others => 'X');
        end case;
 end process;

 process (PC, IXR_tmp, ACC_tmp, bus_mode)
 begin
        case bus_mode is
        when "000" => Y0 <= (others => '0');
        when "001" => Y0 <= PC;
        when "010" => Y0 <= (others => '0');
        when "011" => Y0 <= (others => '0');
        when "100" => Y0 <= PC;
        when "101" => Y0 <= IXR_tmp;
        when "110" => Y0 <= ACC_tmp;
        when "111" => Y0 <= (others => '0');
        when others => Y0 <= (others => 'X');
        end case;
 end process;

 process (reset, T3)
 begin
 if (reset = '0' or reset = 'L') then
        IXR <= "00000000";
-- elsif rising_edge(T3) then
  elsif (T3'event and T3 = '1') then
        IXR <= ALU;
 end if;
 end process;


 process (reset, clock)
 begin
 if (reset = '0' or reset = 'L') then
        IXR_tmp <= "00000000";
-- elsif rising_edge(clock) then
  elsif (clock'event and clock = '1') then
        IXR_tmp <= IXR;
 end if;
 end process;

 process (reset, T4)
 begin
 if (reset = '0' or reset = 'L') then
        ACC <= "00000000";
-- elsif rising_edge(T4) then
  elsif (T4'event and T4 = '1') then
        ACC <= ALU;
 end if;
 end process;

 process (reset, T2)
 begin
 if (reset = '0' or reset = 'L') then
        zero_flag <= '0';
-- elsif  rising_edge(T2) then
  elsif (T2'event and T2 = '1') then
        zero_flag <= Zero0;
 end if;
 end process;

 process (reset, clock)
 begin
 if (reset = '0' or reset = 'L') then
        ACC_tmp <= "00000000";
-- elsif rising_edge(clock) then
  elsif (clock'event and clock = '1') then
        ACC_tmp <= ACC;
 end if;
 end process;

 process (reset, T2)
 begin
 if (reset = '0' or reset = 'L') then
        carry_flag <= '0';
-- elsif rising_edge(T2) then
  elsif (T2'event and T2 = '1') then
        carry_flag <= Carry0;
 end if;
 end process;

 process (zero_flag, carry_flag, IR(0))
 begin
        if (IR(0) = '0') then 
        	net_1 <= zero_flag;
        else 
		net_1 <= carry_flag;
	end if;
 end process;

 S1 <= not(CH(0)) or (not(CH(1)) and (IR(1) xor net_1));
 T2 <= CH(2) and clock;
 T4 <= clock and CH(4);
 T3 <= clock and CH(3);

 process (ALU)
 begin
        if (ALU = "00110000") then
                n_eq0 <= '1';
        else
                n_eq0 <= '0';
        end if;
 end process;

 net_3 <= IR(0) and S1;
 net_2 <= n_eq0 and not(CH(1));
 error_out <= net_2 and net_3 and not(carry_flag) and zero_flag and net_1 ;

end RTL;