address.vhd

基于bpsk的vhdl语言编程与性能仿真

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity address is
port(
      d:in std_logic;
      fclk:in std_logic;
      ass:out std_logic_vector(5 to 0)
       );
end address;
architecture b of address is
signal temp:std_logic_vector(9 downto 0);
begin
   process(fclk)
   begin
   if(fclk'event and fclk='1')then
   if temp="1111111111" then
      temp<="0000000000";
     else 
       if d='0' then
      temp<=temp+"0000000001";
      else 
       temp<=temp+"0000000100";
   end if;
   end if;
   end if;
end process;
ass<=temp(9 to 4);
end b;