clk_div.vhd.bak

VHDL语言描述

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
	port(
		clk50M: in std_logic;
		clk1M,clk10K,clk100,clk500K: out std_logic
	);
end clk_div;
architecture bhv of clk_div    is
	signal clk1M_1:std_logic;
	signal clk500K_1,clk10K_1,clk100_1: std_logic;
	begin
		--------1M clk---------------
		process(clk50M)
			variable cnt: std_logic_vector(4 downto 0);
			begin
				if clk50M'event and clk50M='1' then
					if cnt="11000" then
						clk1M_1<=not clk1M_1;
						cnt:=0;
					else cnt:=cnt+'1';
					end if;
				end if;
		end process;
		-------500k---------------------
		process(clk1M_1) begin
			if clk1M_1'event and clk1M_1='1' then
				clk500K_1<=not clk500K_1;
			end if;
		end process;
		---------10k---------------
		process(clk500K_1) 
			variable cnt: std_logic_vector(4 downto 0);
			begin
			if clk500K_1'event and clk500K_1='1' then
				if cnt="11000" then
					clk10K_1<=not clk10K_1;
					cnt:=0;
				else cnt:=cnt+1;
				end if;
			end if;
		end process;
		-----------100hz------------
		process(clk10K_1) 
			variable cnt: std_logic_vector(5 downto 0);
			begin
			if clk10K_1'event and clk10K_1='1' then
				if cnt="110001" then
					clk100_1<=not clk100_1;
					cnt:=0;
				else cnt:=cnt+1;
				end if;
			end if;
		end process;
		----------------------------------
		clk1M<=clk1M_1;
		clk500K<=clk500K_1;
		clk10K<=clk10K_1;
		clk100<=clk100_1;
end bhv;