ps.vhd

ps2 vhdl 实现键盘输入 数码管显示ascii码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 entity ps is
port(
k_data: in std_logic;
clk:in std_logic;
PA     :buffer std_logic_vector(7 downto 0);
"data   :out std_logic_vector(7 downto 0);
INTR2: out std_logic"
CS     :std_logic;
RD     :in std_logic;
ZHJS:   buffer std_logic;
BIN: out std_logic_vector(7 downto 0);
);
end ps;
architecture behavior of ps is
signal tmpbitvector:std_logic_vector(11 downto 0):="000000000000";
signal enable: std_logic:='0';
signal SavedPA:std_logic_vector(7 downto 0);


begin
process(CS,clk)
variable started:std_logic:='0';
variable count:integer range 0 to 11 :=0;
begin
if CS='1' then ZHJS<='0';count:=0;
elsif  falling_edge(clk) then
       tmpbitvector(count)<=k_data;
       if count=10 then ZHJS<='0';
       else ZHJS<='1';
       end if;
       if count=11 then count:=1;
       else count:=count+1;
       end if;
end if;
       if(count>1 and count<10) then started:='1';
       else started:='0';
       end if;
             enable<=started;
end process;
     PA<="00000000" when CS='1' or enable ='1'else
          tmpbitvector(8 downto 1);
process(PA,tmpbitvector)
begin
BIN<=PA;
"未知LED连接方式,包括段选和译码规则"
end process;
"ReadData:
process(RD)
begin
     if CS='1' or RD='1' then data<=""ZZZZZZZZ"";
     else data<=SavedPA;
     end if;
end process readdata;
GenerateINTR2:
process(ZHJS,RD,CS)
begin
     if CS='1' OR RD='0' then INTR2<='0';
     elsif falling_edge(ZHJS) then
           SavedPA<=PA;INTR2<='1';
     end if;
end process GenerateINTR2;"
end behavior;