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https://www.eeworm.com/dl/fpga/doc/32719.html
教程资料
UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portio ...
https://www.eeworm.com/dl/kbcluoji/40395.html
可编程逻辑
UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portio ...
https://www.eeworm.com/dl/628/178964.html
编译器/解释器
encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in
encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
...
https://www.eeworm.com/dl/663/172732.html
VHDL/FPGA/Verilog
<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.
<Floating Point Unit Core>
fpupack.vhd
pre_norm_addsub.vhd
addsub_28.vhd
post_norm_addsub.vhd
pre_norm_mul.vhd
mul_24.vhd
vcom serial_mul.vhd
post_norm_mul.vhd
pre_norm_div.vhd
serial_div.vhd
post_norm_div.vhd
pre_norm_sqrt.vhd
sqrt.vhd
post_norm_sqrt.vhd
comppack.vhd
fpu.vhd
** ...
https://www.eeworm.com/dl/502/29207.html
单片机编程
基于C8051F060的数据采集存储系统的设计
介绍一种基于C8051F060单片机和NAND Flash的数据采集存储系统，该系统可实现3路信号采样，每路采样率为5KS/s,通过异步串行通信接口实现数据传输。并详细说明系统的软件设计。
Abstract:
&nbsp;An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The s ...
https://www.eeworm.com/dl/663/226442.html
VHDL/FPGA/Verilog
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with ...
https://www.eeworm.com/dl/855034.html
技术资料
verilog串口通信程序
verilog串口通信程序
网上关于RS-232的异步收发介绍得很多，最近没事学着摸索用ModelSim来做时序仿真，就结合网上的参考资料和自己的琢磨，做了这个东西。
针对我这个小程序结合FPGA的开发流程，主要走了以下几步：
1. 文本程序输入（Verilog HDL）
2. 功能仿真（ModelSim，查看逻辑功能是否正确，要 ...
https://www.eeworm.com/dl/894744.html
技术资料
电动汽车测试台架控制系统设计
设计一种以单片机为核心的电动汽车测试台架控制系统,用于对电动机等电动汽车关键零部件的性能测试。该系统主要包括主控板和按键板,主控板有232通讯电路、485通讯电路、CAN通讯电路、AD采集电路、继电器控制电路、数据存储电路、实时时钟电路、单片机及其周围电路;按键板有按键输入及按键指示灯控制电路 ...
https://www.eeworm.com/dl/663/406293.html
VHDL/FPGA/Verilog
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro
The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file ...
https://www.eeworm.com/dl/504/12618.html
VHDL/Verilog/EDA源码
SDRAM读写控制的实现与Modelsim仿真
软件开发环境：ISE 7.1i
硬件开发环境：红色飓风II代－Xilinx版
1. 本实例用于控制开发板上面的SDRAM完成读写功能；
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。
2. part1目录是使用Modelsim仿真的工程；
3. part2目录是在开发版上 ...