controller.v

6x6 bit digital multiplier

`define s0 2'b00
`define s1 2'b01
`define s2 2'b10
`define s3 2'b11
module controller(CLK,RST,r,start,c1,c2,done,CW);
input CLK,RST,r,start,c1,c2;
output done;
reg done;
output [5:0] CW;
reg [5:0] CW;
reg [1:0] state;
always @(posedge CLK or posedge RST) 
    
    if (RST)                              state <=  `s0;
    else if (start == 0)                  state <=  `s0;
    else if (state != `s1)  
     begin              
         if (CW == 6'b000000)             state <=  `s0;
         else                             state <=  `s1;
     end    
    else if (r == 1'b0)                   state <=  `s0;
    else if ((c1 == 1'b0)&(c2 == 1'b1))   state <=  `s2; 
    else if ((c1 == 1'b1)&(c2 == 1'b0))   state <=  `s3;
    else                                  state <=  `s1;
                
always @ (c1,c2,state,r,start) begin
    if (state == `s0) begin
        if (start == 0) begin
            CW <= 6'b000000;
            done <= 0;
        end
        else if (done == 1'b0) begin
            CW <= 6'b000111;
            done <= 0;
        end
    end
    if (state == `s1) begin
        if (r == 1'b1) begin
            if ((c1 == 0)&(c2 == 1)) begin
                CW <= 6'b100001;
                done <= 0;
            end
            if ((c1 == 1)&(c2 == 0)) begin
                CW <= 6'b101001;
                done <= 0;
            end
            if ((c1 == 0)&(c2 == 0)) begin
                CW <= 6'b110100;
                done <= 0;
            end
            if ((c1 == 1)&(c2 == 1)) begin
                CW <= 6'b110100;
                done <= 0;
            end
        end
        else begin
                CW <=6'b000000;
                done <= 1;
        end
    end
    if (state == `s2) begin
        CW <= 6'b110100;
        done <= 0;
    end
    if (state == `s3) begin
        CW <= 6'b110100;
        done <= 0;
    end
end           
endmodule