multiplier.v

来自「6x6 bit digital multiplier」· Verilog 代码 · 共 17 行

module multiplier (clk,reset,start,done, Z1);
input clk,reset,start;
wire [5:0] A,B;
assign A = 6'b000001;
assign B = 6'b000001;
output done;
wire done;
//output [11:0] Z;
output [2:0] Z1;
wire [2:0] Z1;
wire [11:0] Z;
wire r,SO;
wire [5:0] cw;
assign Z1 = Z[2:0];
datapath datapath1 (A,B,Z[11:6],Z[5:0],SO,clk,reset,r,cw);
controller controller1 (clk,reset,r,start,Z[0],SO,done,cw);
endmodule