shift6.v

来自「6x6 bit digital multiplier」· Verilog 代码 · 共 30 行

module shift6(CLK,RST,LD,SF,SI,D,SO,Q);
input CLK,RST,LD,SF,SI;
input [5:0] D;
output SO;
output [5:0] Q;
reg SO;
reg [5:0] Q; 
wire [5:0] temp;
wire tempO;
or (temp[5], SF&SI,   ~SF&D[5]&LD, ~SF&~LD&Q[5]);
or (temp[4], SF&Q[5], ~SF&D[4]&LD, ~SF&~LD&Q[4]);
or (temp[3], SF&Q[4], ~SF&D[3]&LD, ~SF&~LD&Q[3]);
or (temp[2], SF&Q[3], ~SF&D[2]&LD, ~SF&~LD&Q[2]);
or (temp[1], SF&Q[2], ~SF&D[1]&LD, ~SF&~LD&Q[1]);
or (temp[0], SF&Q[1], ~SF&D[0]&LD, ~SF&~LD&Q[0]);
or (tempO, SF&Q[0], ~SF&SO);
always@(posedge CLK or posedge RST) 
begin
    if (RST) 
        begin
        Q <= 6'b0;
        SO <= 0;
        end
    else 
        begin    
        Q <=  temp;
        SO <=  tempO;
        end
end
endmodule