datapath.v

来自「6x6 bit digital multiplier」· Verilog 代码 · 共 34 行

module datapath (A,B,Zhout,Zlout,SOout,clk, reset,r,CW);
input [5:0] A,B;
input clk, reset;
input [5:0] CW;
output [5:0] Zhout,Zlout;
output r,SOout;

wire [5:0] m1out,Zhout,Zlout,addout;
wire [3:0] m2out,r3out,decrout;
wire SOout,SO1out,r;
wire [5:0] temp;

mux6 m1(6'b000000,addout,CW[5],m1out);

shift6 r1(clk,reset,CW[0],CW[4],Zhout[5],m1out,SO1out,Zhout);
shift6 r2(clk,reset,CW[1],CW[4],Zhout[0],B,SOout,Zlout);

xor (temp[0], A[0], CW[3]);
xor (temp[1], A[1], CW[3]);
xor (temp[2], A[2], CW[3]);
xor (temp[3], A[3], CW[3]);
xor (temp[4], A[4], CW[3]);
xor (temp[5], A[5], CW[3]);
CLAadder a1(Zhout,temp,CW[3],addout);

mux4 m2(4'b0110,decrout,CW[5],m2out);

reg4 r3(clk,CW[2],reset,m2out,r3out);

decr4 d1(r3out,decrout);

oring o1(r3out,r);

endmodule