mux4.v

来自「6x6 bit digital multiplier」· Verilog 代码 · 共 8 行

module mux4(A,B,sel,Y);
input [3:0] A;
input [3:0] B;
input sel;
output [3:0] Y;
wire [3:0] Y;
assign Y = sel? B:A;
endmodule