decr4.v

来自「6x6 bit digital multiplier」· Verilog 代码 · 共 15 行

module decr4 (A, Y);
input [3:0] A;
output [3:0] Y;
wire [3:0] Y;
wire [3:0] C;
assign C[0]=1'b0;
assign C[1]=(A[0] | C[0]);
assign C[2]=(A[1] | C[1]);
assign C[3]=(A[2] | C[2]);
assign Y[0]=(~(A[0]) ^ C[0]);
assign Y[1]=(~(A[1]) ^ C[1]);
assign Y[2]=(~(A[2]) ^ C[2]);
assign Y[3]=(~(A[3]) ^ C[3]);
endmodule