myclock.map.qmsg

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h_alarm clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l_alarm clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h_alarm clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l_alarm clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h_alarm clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l_alarm clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h_alarm clk_and_modify.vhd(143) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "choose_state clk_and_modify.vhd(147) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(147): signal choose_state is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 147 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(39) " "Info: VHDL Case Statement information at display.vhd(39): OTHERS choice is never selected" {  } { { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mux_out display.vhd(42) " "Warning: VHDL Process Statement warning at display.vhd(42): signal mux_out is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 42 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "display.vhd(53) " "Info: VHDL Case Statement information at display.vhd(53): OTHERS choice is never selected" {  } { { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 53 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "c:/altera/quartus41/libraries/megafunctions/look_add.tdf" "look_add" "" { Text "c:/altera/quartus41/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "19 " "Info: Ignored 19 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "19 " "Info: Ignored 19 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "distribute_frq:u1\|q3\[0\] display:u4\|q\[0\] " "Info: Duplicate register distribute_frq:u1\|q3\[0\] merged to single register display:u4\|q\[0\]" {  } { { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 31 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "revert " "Info: Promoted clock signal driven by pin revert to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "157 " "Info: Implemented 157 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "128 " "Info: Implemented 128 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "6 " "Info: Implemented 6 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 71 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 71 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 30 17:07:22 2007 " "Info: Processing ended: Sun Dec 30 17:07:22 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}