myclock.map.qmsg

来自「用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小」· QMSG 代码 · 共 95 行 · 第 1/3 页

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l_alarm clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h_alarm clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l_alarm clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h_alarm clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l_alarm clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h_alarm clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l_alarm clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h_alarm clk_and_modify.vhd(140) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l_alarm clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h_alarm clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_l_alarm clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_h_alarm clk_and_modify.vhd(141) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_h_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l_alarm clk_and_modify.vhd(142) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_l_alarm is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 142 0 0 } }  } 0}