myclock.map.qmsg

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 30 17:07:11 2007 " "Info: Processing started: Sun Dec 30 17:07:11 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off myclock -c myclock " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off myclock -c myclock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myclock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file myclock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 myclock-arch " "Info: Found design unit 1: myclock-arch" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/myclock.vhd" "myclock-arch" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/myclock.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 myclock " "Info: Found entity 1: myclock" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/myclock.vhd" "myclock" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/myclock.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_and_modify.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_and_modify.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_and_modify-arch " "Info: Found design unit 1: clk_and_modify-arch" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "clk_and_modify-arch" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 25 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_and_modify " "Info: Found entity 1: clk_and_modify" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "clk_and_modify" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-arch " "Info: Found design unit 1: display-arch" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/display.vhd" "display-arch" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/display.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/display.vhd" "display" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/display.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "distribute_frq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file distribute_frq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 distribute_frq-arch " "Info: Found design unit 1: distribute_frq-arch" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/distribute_frq.vhd" "distribute_frq-arch" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/distribute_frq.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 distribute_frq " "Info: Found entity 1: distribute_frq" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/distribute_frq.vhd" "distribute_frq" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/distribute_frq.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "time_form.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file time_form.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 time_form-arch " "Info: Found design unit 1: time_form-arch" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/time_form.vhd" "time_form-arch" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/time_form.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 time_form " "Info: Found entity 1: time_form" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/time_form.vhd" "time_form" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/time_form.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "choose_state_signal myclock.vhd(112) " "Warning: VHDL Process Statement warning at myclock.vhd(112): signal choose_state_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 112 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sel_signal myclock.vhd(113) " "Warning: VHDL Process Statement warning at myclock.vhd(113): signal sel_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 113 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mux_o_signal myclock.vhd(114) " "Warning: VHDL Process Statement warning at myclock.vhd(114): signal mux_o_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mux_o_signal myclock.vhd(115) " "Warning: VHDL Process Statement warning at myclock.vhd(115): signal mux_o_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sel_signal myclock.vhd(117) " "Warning: VHDL Process Statement warning at myclock.vhd(117): signal sel_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mux_o_signal myclock.vhd(118) " "Warning: VHDL Process Statement warning at myclock.vhd(118): signal mux_o_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mux_o_signal myclock.vhd(119) " "Warning: VHDL Process Statement warning at myclock.vhd(119): signal mux_o_signal is in statement, but is not in sensitivity list" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 119 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "myclock.vhd(121) " "Info: VHDL Case Statement information at myclock.vhd(121): OTHERS choice is never selected" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 121 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "y distribute_frq.vhd(16) " "Warning: VHDL Signal Declaration warning at distribute_frq.vhd(16): ignored default value for signal y" {  } { { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "y2 distribute_frq.vhd(17) " "Warning: VHDL Signal Declaration warning at distribute_frq.vhd(17): ignored default value for signal y2" {  } { { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 17 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "clk_and_modify.vhd(88) " "Info: VHDL Case Statement information at clk_and_modify.vhd(88): OTHERS choice is never selected" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 88 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "clk_and_modify.vhd(123) " "Info: VHDL Case Statement information at clk_and_modify.vhd(123): OTHERS choice is never selected" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(136) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(136) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(136) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(136) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "choose clk_and_modify.vhd(136) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal choose is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(137) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(137) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_l clk_and_modify.vhd(137) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal min_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_h clk_and_modify.vhd(137) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal min_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "choose clk_and_modify.vhd(137) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal choose is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_l clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal sec_l is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_h clk_and_modify.vhd(139) " "Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal sec_h is in statement, but is not in sensitivity list" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 139 0 0 } }  } 0}