kd_cpu.v

verilog语言写的8位CPU源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module KD_CPU(data,address_out,CS,WRITE,READ,clk,reset);
     parameter width=8;
		 inout[width-1:0] data;     //数据输出端口
		 output[width-1:0] address_out;  //地址输出端口
 		 output CS;								//读写控制
     output READ;
     output WRITE;

		 input clk;                      //clk
		 input reset;                    //reset
		 wire[width-1:0] data_bus;       //数据总线
		 wire[width-1:0] ALU_out;        //经过ALU处理过后的数据
		 wire[width-1:0] GR_out;         //从通用寄存器GR中引出来的数据
		 wire[width-1:0] IR_out;         //从指令寄存器中引出来的数据(指令)
		 wire[width-1:0] AC_out;         //从累加器中引出的数据
		 //////////////////////
		 //added by zz
		 wire[width-1:0] SPGR_out;         //???
		 wire[2*width-1:0] MU_out;
		 wire[2:0] SP_out;
		 wire[2*width-1:0] quotient;
		 wire[width-1:0]    residue;
		 wire[width-1:0] ZYGR_out;
		 wire[2*width-1:0] ZYGR_outDIV;
		 wire[2:0] ZYGR_address;
		 wire ZYGRLE;
		 wire ZYMULE;
		 wire ZYDIVLE;
		 
		 wire MUE;
		 wire DIVE;
		 wire CS;
		 wire READ;
		 wire WRITE;
     wire SPME1;
		 wire SPCE1;

		 ///////////////////////////
		 wire is_zero;							//
		 wire C_out;							//
		 wire C_in;								//C标志寄存器输入
		 wire Z_out;                     //Z标志寄存器输出


		 wire[width-1:0] AR_address;     //从地址寄存器中引出来的地址
		 wire[width-1:0] PC_address;     //从程序计数器PC引出来的地址
		 wire[2:0] GR_address;				//通用寄存器组的地址
		 wire[4:0] ALU_OP;					//ALU部件的操作码
		 wire[1:0] mux_C_sel;				//C标志寄存器的输入选择控制信号
		 wire[2:0] mux_DB_sel;				//数据总线DB的输入选择控制信号
		 wire mux_AB_sel; 					//
       //defined by zz
       

		 wire CLE;	                     //C标志寄存器使能
		 wire ZLE;								//Z标志寄存器使能
		 wire IRLE;							   //IR使能
		 wire ARLE;								//AR使能
		 wire ACLE;								//AC使能
		 wire GRLE;								//通用寄存器使能
		 wire PCLE;								//PC加载使能
		 wire PCCE;								//PC计数使能
		 wire ALU_C;                     //由ALU产生的进位

     wire[7:0] data_in;
     wire[7:0] data_out;
     assign data_in=(READ=='b0)?data:8'bz;
     assign data=(WRITE=='b0)?data_out:8'bz;
     assign data_out=data_bus;       //读数据总线上的数据
		 assign is_zero=(ALU_out=='b0)?'b1:'b0;  //判“0”逻辑
       
       
       //clock clock(clk);
 
       
		 register #(1) C(.register_out(C_out),.register_in(C_in),.clk(clk),
		                 .reset(reset),.load_enable(CLE));   //
		 register #(1) Z(.register_out(Z_out),.register_in(is_zero),.clk(clk),
		                 .reset(reset),.load_enable(ZLE));   //
       register #(8) IR(.register_out(IR_out),.register_in(data_in),.clk(clk),
		                 .reset(reset),.load_enable(IRLE));   //
		 register #(8) AR(.register_out(AR_address),.register_in(data_bus),.clk(clk),
		                 .reset(reset),.load_enable(ARLE));   //
		 register #(8) AC(.register_out(AC_out),.register_in(data_bus),.clk(clk),
		                 .reset(reset),.load_enable(ACLE));   //
       

       mux4 #(1) mux_C(.mux4_out(C_in),.m0_in(ALU_C),.m1_in(AC_out[0]),
		                 .m2_in(AC_out[7]),.m3_in(1'b0),.sel_in(mux_C_sel));  
							  
		//////////////////////////
		//modified by zz
		 mux8 #(8) mux_DB(.mux8_out(data_bus),.m0_in(AC_out),.m1_in(ALU_out),
		                 .m2_in(data_in),.m3_in(PC_address),.m4_in(SPGR_out),
		                 .m5_in(ZYGR_out),.m6_in(8'b0),.m7_in(8'b0),.sel_in(mux_DB_sel));  
							  //
		/////////////////////////////////
		 mux2 #(8) mux_AB(.mux2_out(address_out),.m0_in(PC_address),
		                  .m1_in(AR_address),.sel_in(mux_AB_sel));
		///////////////////////////////////
		//				  
 		
		 mulit MU(.result(MU_out),.op_a(AC_out),.op_b(GR_out),.MUE(MUE));
		 GR SPGR(.GR_out(SPGR_out),.GR_in(data_bus),.clk(clk),.reset(reset),
		       .GR_address(GR_address),.load_enable(SPGRLE));
		 SP SP(.sp_out(SP_out),.clk(clk),.reset(reset),.minus_enable(SPME1),.plus_enable(SPCE1));
		 
		 /////////

		 GR GR(.GR_out(GR_out),.GR_in(data_bus),.clk(clk),.reset(reset),
		       .GR_address(GR_address),.load_enable(GRLE));
		 ZYGR ZYGR(.ZYGR_out(ZYGR_out),.ZYGR_outDIV(ZYGR_outDIV),.ZYGR_in(data_bus),.ZYGR_inMU(MU_out),
		           .ZYGR_inS(quotient),.ZYGR_inY(residue),.clk(clk),.reset(reset),.ZYGR_address(ZYGR_address),
                 .load_enable(ZYGRLE),.MUL_outenable(ZYMULE),.DIV_outenable(ZYDIVLE),
                 .DIVenable(DIVE));
      
		 DIV  DIV(.quotient(quotient),.residue(residue),.dividend(ZYGR_outDIV),.divisor(AC_out),.DIVE(DIVE));
		 
		 ALU ALU(.ALU_O(ALU_out),.ALU_C(ALU_C),.C_in(C_out),.op(ALU_OP),
		         .AC_in(AC_out),.GR_in(GR_out));           
		 PC PC(.pc_out(PC_address),.pc_in(data_bus),.clk(clk),.reset(reset),
		       .load_enable(PCLE),.count_enable(PCCE));    
		       
		 CU CU(.CLE(CLE),.ZLE(ZLE),.ALU_OP(ALU_OP),.ACLE(ACLE),
		       .GR_address(GR_address),.GRLE(GRLE),.IRLE(IRLE),
				 .ARLE(ARLE),.PCLE(PCLE),.PCCE(PCCE),
				 .SPGR_address(SP_out),.SPGRLE(SPGRLE),.SPCE(SPCE1),.SPME(SPME1),
				 .MUE(MUE),.DIVE(DIVE),.ZYGRLE(ZYGRLE),.ZYMULE(ZYMULE),.ZYDIVLE(ZYDIVLE),.ZYGR_address(ZYGR_address),
				 .mux_C_sel(mux_C_sel),
				 .mux_DB_sel(mux_DB_sel),.mux_AB_sel(mux_AB_sel),
				 .CS(CS),.READ(READ),.WRITE(WRITE),.sp_in(SP_out),.clk(clk),
				 .reset(reset),.C_in(C_out),.Z_in(Z_out),.IR_in(IR_out));//
   
endmodule