cu.v

verilog语言写的8位CPU源代码

                          begin
                             GR_address=IR_in[2:0];    //GR
                             ALU_OP=IR_in[7:3];        //ALU operation code
                             mux_DB_sel='b001;         //data from ALU_O
                             ACLE='b1;                 //AC load enable
                             CLE='b1;                  //C flag load enable
                             ZLE='b1;                  //Z flag load enable
                             
                             if(IR_in[7:3]=='b01010)   //SHCR AC,GR
                                 mux_C_sel='b10;       //C flag choose AC_out[7]
                             if(IR_in[7:3]=='b01011)   //SHCL AC,GR
                                 mux_C_sel='b01;       //C flag shoose AC_out[0]
                                 
                             ////////The work done in FIRST state 
                               mux_AB_sel='b0;      //Address from PC  
                               CS='b0;              //Select the Memory
                               READ='b0;            //Read enable        
                               IRLE='b1;            //IR load enable                 
                               PCCE='b1;            //PC increase enable
                            ////////////////////////////
                            
                          end
                      //
                      'b01100,//JMP Mi
                      'b01101,//JNZ Mi
                      'b01110://JNC Mi
                          begin
                             mux_AB_sel='b0;     //memory adress from PC
                             CS='b0;             //memory enable
                             READ='b0;//         //Read enable
                             mux_DB_sel='b010;   //data from memory
                             case(IR_in[4:3])
                             'b00:PCLE='b1;                      //PC load enable 
                             'b01:begin PCLE=!Z_in;PCCE='b1;end  //PC load or increase 
                             'b10:begin PCLE=!Z_in;PCCE='b1;end  //PC load or increase 
                             endcase
                          end
                          'b10000://call
                          begin
                              mux_DB_sel='b011;        //data comes from pc_address
                              SPGR_address=sp_in;      //adress from SP
                              SPGRLE='b1;              //load enable
                               
                          end
                          'b10001://return
                          begin      
                              SPGR_address=sp_in-1;    //SPGR address
                              mux_DB_sel='b100;        //data from spGR
                              PCLE='b1;
                          end
                          'b10010://MULTIPLY
                          begin
                              GR_address=IR_in[2:0];
                              MUE='b1;
                              ZYGRLE='b1;
                              ZYMULE='b1;   
                            ////////The word done in FIRST state 
                               mux_AB_sel='b0;   //Address from PC  
                               CS='b0;           //Select the Memory
                               READ='b0;         //Read enable        
                               IRLE='b1;         //IR load enable                 
                               PCCE='b1;         //PC increase enable
                            ////////////////////////////
                          end
                          'b10011://DIV
                          begin
                              DIVE='b1;
                              ZYGRLE='b1;//wirite enable
                              ZYDIVLE='b1;
                             
                              ////////The word done in FIRST state 
                               mux_AB_sel='b0;   //Address from PC  
                               CS='b0;           //Select the Memory
                               READ='b0;         //Read enable        
                               IRLE='b1;         //IR load enable                 
                               PCCE='b1;         //PC increase enable
                            ////////////////////////////  
                              
                          end
                          'b10100://mov AC to ZYGR
                          begin
                              mux_DB_sel='b000;
                              ZYGR_address=IR_in[2:0];
                              ZYGRLE=1; //write ennable 
                              ////////The word done in FIRST state 
                               mux_AB_sel='b0;   //Address from PC  
                               CS='b0;           //Select the Memory
                               READ='b0;         //Read enable        
                               IRLE='b1;         //IR load enable                 
                               PCCE='b1;         //PC increase enable
                            ////////////////////////////                           
                          end
                          
                          'b10101://mov ZYGR to AC
                          begin
                              ZYGR_address=IR_in[2:0];
                              mux_DB_sel='b101;
                           
                              ACLE='b1;  
                              ////////The word done in FIRST state 
                               mux_AB_sel='b0;   //Address from PC  
                               CS='b0;           //Select the Memory
                               READ='b0;         //Read enable        
                               IRLE='b1;         //IR load enable                 
                               PCCE='b1;         //PC increase enable
                            ////////////////////////////                      
                          end
                        'b10110://push AC
                           begin
                              mux_DB_sel='b000;        //data comes from AC_out
                              SPGR_address=sp_in;      //adress from SP
                              SPGRLE='b1;              //load enable 
                          end 
                        'b10111://pop AC   
                        begin                    
                              SPGR_address=sp_in-1;    //SPGR address
                              mux_DB_sel='b100;        //data from spGR
                              ACLE='b1;
                          end
                        'b11000://loop
                        begin
                            GR_address=IR_in[2:0];
                            ALU_OP=IR_in[7:3];       //GR[0]--
                            mux_DB_sel='b001;        //data from ALU_O
                            GRLE='b1;                  
                        end
                  endcase
        end
        THIRD:
           begin             
              case(IR_in[7:3])
                  'b00000,  //LOAD
                  'b00001:
                     begin
                       mux_AB_sel='b1;          //adress comes from AR 
                       if(!IR_in[3])
                          begin
                             CS='b0;             //enable
                             READ='b0;           //read model
                             mux_DB_sel='b010;   //data comes from memory
                             ACLE='b1;           //AC load enble
                          end
                       else
                          begin
                             mux_DB_sel='b000;  //data comes from AC
                             CS='b0;            //enable
                             WRITE='b0;         //write ezble
                      end
                    end
                   'b10000://call
                   begin
                       SPCE='b1;                  //sp++ 
                       mux_AB_sel='b0;            //address from PC
                       CS='b0;                    //memory enable
                       READ='b0;                  //read enable
                       mux_DB_sel='b010;          //data comes from memory
                       PCLE='b1;
                   end
                   'b10001:  //return
                   begin
                       SPME='b1;                   //sp decrease enable
                       PCCE='b1; 
                   end
                   'b10110://push AC
                              SPCE='b1;                  //sp++ 
                   'b10111://pop AC                       
                              SPME='b1;                   //sp decrease enable
                   'b11000://loop
                        begin
                            if(z_in=='b0)
                            begin
                               GR_address='b001;//pc from GR[1]
                               mux_DB_sel='b110;//data from GR_out
                               PCLE='b1;
                           end
                           else
                           begin
                               PCLE='b0;
                           end              
                        end
             endcase
         end
         default:
         READ='b1;
    endcase
  end


endmodule