lcd.vhd

来自「这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器」· VHDL 代码 · 共 46 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is
    Port (A : in  STD_LOGIC_VECTOR(0 to 3);
           B : in  STD_LOGIC_VECTOR(0 to 3);
			  Cin : in  STD_LOGIC;
           D : out STD_LOGIC_VECTOR(0 to 6);
			EN :out STD_LOGIC_VECTOR(0 to 8)

);
end lcd;

architecture Behavioral of lcd is
signal S:STD_LOGIC_VECTOR(0 to 3);
signal Cout:STD_LOGIC;
COMPONENT f_fadd
port( A : in  STD_LOGIC_VECTOR(0 to 3);
           B : in  STD_LOGIC_VECTOR(0 to 3);
			  Cin : in  STD_LOGIC;
           S : out STD_LOGIC_VECTOR(0 to 3);
			  Cout : out STD_LOGIC
			 );
END COMPONENT;
begin
u1: f_fadd PORT MAP (A,B,Cin,S,Cout);

WITH s SELECT
D <= "1111110" WHEN "0000",--0
     "0110000" WHEN "0001",--1
     "1101101" WHEN "0010",--2
     "1111001" WHEN "0011",--3
     "0110011" WHEN "0100",--4
     "1011011" WHEN "0101",--5
     "1011111" WHEN "0110",--6
     "1110000" WHEN "0111",--7
     "1111111" WHEN "1000",--8
     "1111011" WHEN "1001",--9	  
     "0000000" WHEN OTHERS; 
EN<="000000010";
end Behavioral;