f_fadd.vhd

来自「这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity f_fadd is
    Port ( A : in  STD_LOGIC_VECTOR(0 to 3);
           B : in  STD_LOGIC_VECTOR(0 to 3);
			  Cin : in  STD_LOGIC;
           S : out STD_LOGIC_VECTOR(0 to 3);
			  Cout : out STD_LOGIC
			 );
end f_fadd;

architecture Behavioral of f_fadd is
signal C:STD_LOGIC_VECTOR(0 to 2);
COMPONENT f_adder
port(ain,bin,cin  : IN STD_LOGIC;
         cout,sum   : OUT STD_LOGIC);
END COMPONENT;
begin
u1: f_adder PORT MAP (A(3),B(3),Cin,C(0),S(3));
u2: f_adder PORT MAP (A(2),B(2),C(0),C(1),S(2));
u3: f_adder PORT MAP (A(1),B(1),C(1),C(2),S(1));
u4: f_adder PORT MAP (A(0),B(0),C(2),Cout,S(0));

end Behavioral;