f_adder.vhd

来自「这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器」· VHDL 代码 · 共 23 行

 LIBRARY  IEEE;  
 USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY f_adder IS
   PORT (ain,bin,cin  : IN STD_LOGIC;
         cout,sum   : OUT STD_LOGIC );
 END f_adder;
 ARCHITECTURE fd1 OF f_adder IS
   COMPONENT adder
     PORT (  a,b :  IN STD_LOGIC; 
       co,so :  OUT STD_LOGIC);
   END COMPONENT;
   COMPONENT or2a
      PORT (a,b : IN STD_LOGIC; 
                c : OUT STD_LOGIC);
   END COMPONENT;
SIGNAL d,e,f  :  STD_LOGIC; 
  BEGIN
   u1 : adder PORT MAP(a=>ain,b=>bin,co=>d,so=>e);    
   u2 : adder PORT MAP(a=>e,b=>cin,co=>f,so=>sum);
   u3 : or2a PORT MAP(a=>d,b=>f,c=>cout);
 END fd1;