adder.vhd

来自「这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器」· VHDL 代码 · 共 15 行

LIBRARY  IEEE;    
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY adder IS 
  PORT (
		a, b : IN STD_LOGIC;  
        co, so : OUT STD_LOGIC
);  
END adder;     
ARCHITECTURE fh1 OF adder is  
BEGIN   
  so <= NOT(a XOR (NOT b)) ;
  co <= a AND b ;  
END fh1;