or2a.vhd

来自「这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器」· VHDL 代码 · 共 12 行

 LIBRARY  IEEE ;   
 USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY or2a IS
   PORT (a, b :IN STD_LOGIC; 
              c : OUT STD_LOGIC );
 END or2a;
 ARCHITECTURE one OF or2a IS
   BEGIN
   c <= a OR b ;    			
 END one;