dds_new.sim.rpt
来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· RPT 代码 · 共 337 行 · 第 1/5 页
RPT
337 行
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+-------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+-------------------------------------------------------------------------------------------------+
; |dds_new|sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ALTSYNCRAM ;
+-------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 0.00 % ;
; Total nodes checked ; 625 ;
; Total output ports checked ; 625 ;
; Total output ports with complete 1/0-value coverage ; 0 ;
; Total output ports with no 1/0-value coverage ; 625 ;
; Total output ports with no 1-value coverage ; 625 ;
; Total output ports with no 0-value coverage ; 625 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------+
; |dds_new|A[31] ; |dds_new|A[31] ; pin_out ;
; |dds_new|A[30] ; |dds_new|A[30] ; pin_out ;
; |dds_new|A[29] ; |dds_new|A[29] ; pin_out ;
; |dds_new|A[28] ; |dds_new|A[28] ; pin_out ;
; |dds_new|A[27] ; |dds_new|A[27] ; pin_out ;
; |dds_new|A[26] ; |dds_new|A[26] ; pin_out ;
; |dds_new|A[25] ; |dds_new|A[25] ; pin_out ;
; |dds_new|A[24] ; |dds_new|A[24] ; pin_out ;
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