research.tan.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "ITDB_TH_RESULT" "key_buffer:comb_4\|state.s3 change clk -1.209 ns register " "Info: th for register \"key_buffer:comb_4\|state.s3\" (data pin = \"change\", clock pin = \"clk\") is -1.209 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns key_buffer:comb_4\|state.s3 2 REG LC_X10_Y4_N4 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.s3'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.656 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 54.49 % " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 45.51 % " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.249 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns change 1 PIN PIN_42 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 4; PIN Node = 'change'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { change } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.056 ns) + CELL(1.061 ns) 5.249 ns key_buffer:comb_4\|state.s3 2 REG LC_X10_Y4_N4 2 " "Info: 2: + IC(3.056 ns) + CELL(1.061 ns) = 5.249 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.s3'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "4.117 ns" { change key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns 41.78 % " "Info: Total cell delay = 2.193 ns ( 41.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.056 ns 58.22 % " "Info: Total interconnect delay = 3.056 ns ( 58.22 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "5.249 ns" { change key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "5.249 ns" { change change~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 3.056ns } { 0.000ns 1.132ns 1.061ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "5.249 ns" { change key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "5.249 ns" { change change~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 3.056ns } { 0.000ns 1.132ns 1.061ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 27 08:46:22 2007 " "Info: Processing ended: Sat Oct 27 08:46:22 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}