clk_div.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 42 行

module clk_div(clk_50MHz,clk_phase,clk_lcd,clk_diff);
input clk_50MHz;
output clk_phase,clk_lcd,clk_diff;
//clk_phase:32*2*2400=153600;-------clk_50MHz/
//clk_diff:2400;-------clk_phase/64;

reg [8:0] qa;
reg [2:0] qb;
reg [2:0] qc;

//origin=171;

assign clk_phase=(qa==511);
assign clk_lcd=(qb==7);
assign clk_diff=(qc==7);

//initial
//begin
//qa=171;
//qb=0;
//end

always @(posedge clk_50MHz)
begin
if(qa==511) qa=171;
else qa=qa+1;
end

always @(posedge clk_phase)
begin
if(qb==7) qb=0;
else qb=qb+1;
end

always @(posedge clk_lcd)
begin
if(qc==7) qc=0;
else qc=qc+1;
end

endmodule