research.tan.qmsg

来自「用vhdl语言实现2DPSK数字传输」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}