📄 research.tan.qmsg

📁 用vhdl语言实现2DPSK数字传输
💻 QMSG
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "generate_led:comb_5\|q\[6\] test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1 clk 4.802 ns " "Info: Found hold time violation between source  pin or register \"generate_led:comb_5\|q\[6\]\" and destination pin or register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1\" for clock \"clk\" (Hold time is 4.802 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.317 ns + Largest " "Info: + Largest clock skew is 7.317 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.136 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns key_buffer:comb_4\|state.s2 2 REG LC_X10_Y4_N8 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N8; Fanout = 3; REG Node = 'key_buffer:comb_4\|state.s2'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.032 ns" { clk key_buffer:comb_4|state.s2 } "NODE_NAME" } "" } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(1.294 ns) 6.376 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass 3 REG LC_X10_Y4_N9 17 " "Info: 3: + IC(0.887 ns) + CELL(1.294 ns) = 6.376 ns; Loc. = LC_X10_Y4_N9; Fanout = 17; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.181 ns" { key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.842 ns) + CELL(0.918 ns) 11.136 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1 4 REG LC_X9_Y10_N3 1 " "Info: 4: + IC(3.842 ns) + CELL(0.918 ns) = 11.136 ns; Loc. = LC_X9_Y10_N3; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "4.760 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 41.93 % " "Info: Total cell delay = 4.669 ns ( 41.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.467 ns 58.07 % " "Info: Total interconnect delay = 6.467 ns ( 58.07 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "11.136 ns" { clk key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "11.136 ns" { clk clk~combout key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } { 0.0ns 0.0ns 1.738ns 0.887ns 3.842ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns generate_led:comb_5\|q\[6\] 2 REG LC_X9_Y7_N2 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N2; Fanout = 3; REG Node = 'generate_led:comb_5\|q\[6\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.656 ns" { clk generate_led:comb_5|q[6] } "NODE_NAME" } "" } } { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 54.49 % " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 45.51 % " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk generate_led:comb_5|q[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout generate_led:comb_5|q[6] } { 0.0ns 0.0ns 1.738ns } { 0.0ns 1.163ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "11.136 ns" { clk key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "11.136 ns" { clk clk~combout key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } { 0.0ns 0.0ns 1.738ns 0.887ns 3.842ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk generate_led:comb_5|q[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout generate_led:comb_5|q[6] } { 0.0ns 0.0ns 1.738ns } { 0.0ns 1.163ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.360 ns - Shortest register register " "Info: - Shortest register to register delay is 2.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generate_led:comb_5\|q\[6\] 1 REG LC_X9_Y7_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N2; Fanout = 3; REG Node = 'generate_led:comb_5\|q\[6\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { generate_led:comb_5|q[6] } "NODE_NAME" } "" } } { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.080 ns) + CELL(0.280 ns) 2.360 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1 2 REG LC_X9_Y10_N3 1 " "Info: 2: + IC(2.080 ns) + CELL(0.280 ns) = 2.360 ns; Loc. = LC_X9_Y10_N3; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|out1'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.360 ns" { generate_led:comb_5|q[6] test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns 11.86 % " "Info: Total cell delay = 0.280 ns ( 11.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.080 ns 88.14 % " "Info: Total interconnect delay = 2.080 ns ( 88.14 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.360 ns" { generate_led:comb_5|q[6] test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { generate_led:comb_5|q[6] test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } { 0.0ns 2.08ns } { 0.0ns 0.28ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "11.136 ns" { clk key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "11.136 ns" { clk clk~combout key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } { 0.0ns 0.0ns 1.738ns 0.887ns 3.842ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk generate_led:comb_5|q[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout generate_led:comb_5|q[6] } { 0.0ns 0.0ns 1.738ns } { 0.0ns 1.163ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.360 ns" { generate_led:comb_5|q[6] test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { generate_led:comb_5|q[6] test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1 } { 0.0ns 2.08ns } { 0.0ns 0.28ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "generate_led:comb_5\|q\[1\] reset clk 2.078 ns register " "Info: tsu for register \"generate_led:comb_5\|q\[1\]\" (data pin = \"reset\", clock pin = \"clk\") is 2.078 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.564 ns + Longest pin register " "Info: + Longest pin to register delay is 5.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_43; Fanout = 8; PIN Node = 'reset'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { reset } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.371 ns) + CELL(1.061 ns) 5.564 ns generate_led:comb_5\|q\[1\] 2 REG LC_X9_Y7_N5 3 " "Info: 2: + IC(3.371 ns) + CELL(1.061 ns) = 5.564 ns; Loc. = LC_X9_Y7_N5; Fanout = 3; REG Node = 'generate_led:comb_5\|q\[1\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "4.432 ns" { reset generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns 39.41 % " "Info: Total cell delay = 2.193 ns ( 39.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.371 ns 60.59 % " "Info: Total interconnect delay = 3.371 ns ( 60.59 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "5.564 ns" { reset generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "5.564 ns" { reset reset~combout generate_led:comb_5|q[1] } { 0.000ns 0.000ns 3.371ns } { 0.000ns 1.132ns 1.061ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns generate_led:comb_5\|q\[1\] 2 REG LC_X9_Y7_N5 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N5; Fanout = 3; REG Node = 'generate_led:comb_5\|q\[1\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.656 ns" { clk generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 54.49 % " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 45.51 % " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout generate_led:comb_5|q[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "5.564 ns" { reset generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "5.564 ns" { reset reset~combout generate_led:comb_5|q[1] } { 0.000ns 0.000ns 3.371ns } { 0.000ns 1.132ns 1.061ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk generate_led:comb_5|q[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout generate_led:comb_5|q[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led_out\[7\] test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1 15.041 ns register " "Info: tco from clock \"clk\" to destination pin \"led_out\[7\]\" through register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1\" is 15.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.136 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns key_buffer:comb_4\|state.s2 2 REG LC_X10_Y4_N8 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N8; Fanout = 3; REG Node = 'key_buffer:comb_4\|state.s2'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.032 ns" { clk key_buffer:comb_4|state.s2 } "NODE_NAME" } "" } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(1.294 ns) 6.376 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass 3 REG LC_X10_Y4_N9 17 " "Info: 3: + IC(0.887 ns) + CELL(1.294 ns) = 6.376 ns; Loc. = LC_X10_Y4_N9; Fanout = 17; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.181 ns" { key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.842 ns) + CELL(0.918 ns) 11.136 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1 4 REG LC_X10_Y10_N1 1 " "Info: 4: + IC(3.842 ns) + CELL(0.918 ns) = 11.136 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "4.760 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 41.93 % " "Info: Total cell delay = 4.669 ns ( 41.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.467 ns 58.07 % " "Info: Total interconnect delay = 6.467 ns ( 58.07 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "11.136 ns" { clk key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "11.136 ns" { clk clk~combout key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } { 0.000ns 0.000ns 1.738ns 0.887ns 3.842ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.529 ns + Longest register pin " "Info: + Longest register to pin delay is 3.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1 1 REG LC_X10_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12 2 COMB LC_X10_Y10_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; COMB Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "0.595 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(2.322 ns) 3.529 ns led_out\[7\] 3 PIN PIN_122 0 " "Info: 3: + IC(0.612 ns) + CELL(2.322 ns) = 3.529 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'led_out\[7\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.934 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.917 ns 82.66 % " "Info: Total cell delay = 2.917 ns ( 82.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.612 ns 17.34 % " "Info: Total interconnect delay = 0.612 ns ( 17.34 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.529 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.529 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } { 0.000ns 0.000ns 0.612ns } { 0.000ns 0.595ns 2.322ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "11.136 ns" { clk key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "11.136 ns" { clk clk~combout key_buffer:comb_4|state.s2 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } { 0.000ns 0.000ns 1.738ns 0.887ns 3.842ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.529 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.529 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } { 0.000ns 0.000ns 0.612ns } { 0.000ns 0.595ns 2.322ns } } }  } 0}
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