research.tan.qmsg

用vhdl语言实现2DPSK数字传输

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "key_buffer:comb_4\|state.s2 " "Info: Detected ripple clock \"key_buffer:comb_4\|state.s2\" as buffer" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key_buffer:comb_4\|state.s2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Detected ripple clock \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\" as buffer" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register key_buffer:comb_4\|state.s3 key_buffer:comb_4\|state.start 304.04 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 304.04 MHz between source register \"key_buffer:comb_4\|state.s3\" and destination register \"key_buffer:comb_4\|state.start\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.389 ns + Longest register register " "Info: + Longest register to register delay is 2.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_buffer:comb_4\|state.s3 1 REG LC_X10_Y4_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.s3'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.511 ns) 1.493 ns key_buffer:comb_4\|state~96 2 COMB LC_X10_Y4_N0 1 " "Info: 2: + IC(0.982 ns) + CELL(0.511 ns) = 1.493 ns; Loc. = LC_X10_Y4_N0; Fanout = 1; COMB Node = 'key_buffer:comb_4\|state~96'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "1.493 ns" { key_buffer:comb_4|state.s3 key_buffer:comb_4|state~96 } "NODE_NAME" } "" } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 2.389 ns key_buffer:comb_4\|state.start 3 REG LC_X10_Y4_N1 2 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.389 ns; Loc. = LC_X10_Y4_N1; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.start'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "0.896 ns" { key_buffer:comb_4|state~96 key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns 46.13 % " "Info: Total cell delay = 1.102 ns ( 46.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.287 ns 53.87 % " "Info: Total interconnect delay = 1.287 ns ( 53.87 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.389 ns" { key_buffer:comb_4|state.s3 key_buffer:comb_4|state~96 key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "2.389 ns" { key_buffer:comb_4|state.s3 key_buffer:comb_4|state~96 key_buffer:comb_4|state.start } { 0.000ns 0.982ns 0.305ns } { 0.000ns 0.511ns 0.591ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns key_buffer:comb_4\|state.start 2 REG LC_X10_Y4_N1 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N1; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.start'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.656 ns" { clk key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 54.49 % " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 45.51 % " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.start } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { clk } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns key_buffer:comb_4\|state.s3 2 REG LC_X10_Y4_N4 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4\|state.s3'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.656 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 54.49 % " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns 45.51 % " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.start } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.389 ns" { key_buffer:comb_4|state.s3 key_buffer:comb_4|state~96 key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "2.389 ns" { key_buffer:comb_4|state.s3 key_buffer:comb_4|state~96 key_buffer:comb_4|state.start } { 0.000ns 0.982ns 0.305ns } { 0.000ns 0.511ns 0.591ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.start } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.819 ns" { clk key_buffer:comb_4|state.s3 } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout key_buffer:comb_4|state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { key_buffer:comb_4|state.start } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { key_buffer:comb_4|state.start } {  } {  } } } { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}