dpsk.tan.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 lcdcont:inst1\|shifter:myshift_low\|qout\[1\] clk_50MHz 14.517 ns " "Info: Found hold time violation between source  pin or register \"DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2\" and destination pin or register \"lcdcont:inst1\|shifter:myshift_low\|qout\[1\]\" for clock \"clk_50MHz\" (Hold time is 14.517 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "17.904 ns + Largest " "Info: + Largest clock skew is 17.904 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 26.063 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to destination register is 26.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[0\] 2 REG LC_X7_Y6_N0 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X7_Y6_N0; Fanout = 4; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[0\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.305 ns) + CELL(0.914 ns) 6.414 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0~127 3 COMB LC_X8_Y6_N7 1 " "Info: 3: + IC(1.305 ns) + CELL(0.914 ns) = 6.414 ns; Loc. = LC_X8_Y6_N7; Fanout = 1; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0~127'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.219 ns" { DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 7.697 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 4 COMB LC_X8_Y6_N0 33 " "Info: 4: + IC(0.772 ns) + CELL(0.511 ns) = 7.697 ns; Loc. = LC_X8_Y6_N0; Fanout = 33; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.476 ns) + CELL(1.294 ns) 11.467 ns DPSK_shell:inst\|clk_div:comb_5\|qb\[2\] 5 REG LC_X11_Y4_N9 2 " "Info: 5: + IC(2.476 ns) + CELL(1.294 ns) = 11.467 ns; Loc. = LC_X11_Y4_N9; Fanout = 2; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qb\[2\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.770 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.740 ns) 13.158 ns DPSK_shell:inst\|clk_div:comb_5\|Equal1 6 COMB LC_X11_Y4_N1 11 " "Info: 6: + IC(0.951 ns) + CELL(0.740 ns) = 13.158 ns; Loc. = LC_X11_Y4_N1; Fanout = 11; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal1'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(1.294 ns) 15.194 ns DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[0\] 7 REG LC_X11_Y4_N6 3 " "Info: 7: + IC(0.742 ns) + CELL(1.294 ns) = 15.194 ns; Loc. = LC_X11_Y4_N6; Fanout = 3; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[0\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.036 ns" { DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] } "NODE_NAME" } } { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.676 ns) + CELL(0.511 ns) 21.381 ns DPSK_shell:inst\|LCM_pre:comb_12\|clk_ser 8 COMB LC_X11_Y4_N2 32 " "Info: 8: + IC(5.676 ns) + CELL(0.511 ns) = 21.381 ns; Loc. = LC_X11_Y4_N2; Fanout = 32; COMB Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|clk_ser'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.187 ns" { DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser } "NODE_NAME" } } { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.764 ns) + CELL(0.918 ns) 26.063 ns lcdcont:inst1\|shifter:myshift_low\|qout\[1\] 9 REG LC_X12_Y6_N6 2 " "Info: 9: + IC(3.764 ns) + CELL(0.918 ns) = 26.063 ns; Loc. = LC_X12_Y6_N6; Fanout = 2; REG Node = 'lcdcont:inst1\|shifter:myshift_low\|qout\[1\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.682 ns" { DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.639 ns ( 33.15 % ) " "Info: Total cell delay = 8.639 ns ( 33.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.424 ns ( 66.85 % ) " "Info: Total interconnect delay = 17.424 ns ( 66.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.063 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.063 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 2.476ns 0.951ns 0.742ns 5.676ns 3.764ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 1.294ns 0.740ns 1.294ns 0.511ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 8.159 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to source register is 8.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcdcont:inst1\|clockdiv:div\|clock_int 2 REG LC_X12_Y3_N9 68 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 68; REG Node = 'lcdcont:inst1\|clockdiv:div\|clock_int'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int } "NODE_NAME" } } { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.046 ns) + CELL(0.918 ns) 8.159 ns DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 3 REG LC_X6_Y6_N6 60 " "Info: 3: + IC(3.046 ns) + CELL(0.918 ns) = 8.159 ns; Loc. = LC_X6_Y6_N6; Fanout = 60; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.964 ns" { lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.37 % ) " "Info: Total cell delay = 3.375 ns ( 41.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 58.63 % ) " "Info: Total interconnect delay = 4.784 ns ( 58.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.159 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.159 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } { 0.000ns 0.000ns 1.738ns 3.046ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.063 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.063 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 2.476ns 0.951ns 0.742ns 5.676ns 3.764ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 1.294ns 0.740ns 1.294ns 0.511ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.159 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.159 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } { 0.000ns 0.000ns 1.738ns 3.046ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.232 ns - Shortest register register " "Info: - Shortest register to register delay is 3.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 1 REG LC_X6_Y6_N6 60 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N6; Fanout = 60; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.641 ns) + CELL(0.591 ns) 3.232 ns lcdcont:inst1\|shifter:myshift_low\|qout\[1\] 2 REG LC_X12_Y6_N6 2 " "Info: 2: + IC(2.641 ns) + CELL(0.591 ns) = 3.232 ns; Loc. = LC_X12_Y6_N6; Fanout = 2; REG Node = 'lcdcont:inst1\|shifter:myshift_low\|qout\[1\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.232 ns" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 18.29 % ) " "Info: Total cell delay = 0.591 ns ( 18.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.641 ns ( 81.71 % ) " "Info: Total interconnect delay = 2.641 ns ( 81.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.232 ns" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "3.232 ns" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 lcdcont:inst1|shifter:myshift_low|qout[1] } { 0.000ns 2.641ns } { 0.000ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.063 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.063 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[2] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_12|wave_low[0] DPSK_shell:inst|LCM_pre:comb_12|clk_ser lcdcont:inst1|shifter:myshift_low|qout[1] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 2.476ns 0.951ns 0.742ns 5.676ns 3.764ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 1.294ns 0.740ns 1.294ns 0.511ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.159 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.159 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } { 0.000ns 0.000ns 1.738ns 3.046ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.232 ns" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 lcdcont:inst1|shifter:myshift_low|qout[1] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "3.232 ns" { DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 lcdcont:inst1|shifter:myshift_low|qout[1] } { 0.000ns 2.641ns } { 0.000ns 0.591ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 reset clk_50MHz -1.386 ns register " "Info: tsu for register \"DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2\" (data pin = \"reset\", clock pin = \"clk_50MHz\") is -1.386 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.440 ns + Longest pin register " "Info: + Longest pin to register delay is 6.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_42 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 8; PIN Node = 'reset'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 200 -104 64 216 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.717 ns) + CELL(0.591 ns) 6.440 ns DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 2 REG LC_X6_Y6_N6 60 " "Info: 2: + IC(4.717 ns) + CELL(0.591 ns) = 6.440 ns; Loc. = LC_X6_Y6_N6; Fanout = 60; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.308 ns" { reset DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 26.75 % ) " "Info: Total cell delay = 1.723 ns ( 26.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.717 ns ( 73.25 % ) " "Info: Total interconnect delay = 4.717 ns ( 73.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.440 ns" { reset DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "6.440 ns" { reset reset~combout DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } { 0.000ns 0.000ns 4.717ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 8.159 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to destination register is 8.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcdcont:inst1\|clockdiv:div\|clock_int 2 REG LC_X12_Y3_N9 68 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 68; REG Node = 'lcdcont:inst1\|clockdiv:div\|clock_int'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int } "NODE_NAME" } } { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.046 ns) + CELL(0.918 ns) 8.159 ns DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2 3 REG LC_X6_Y6_N6 60 " "Info: 3: + IC(3.046 ns) + CELL(0.918 ns) = 8.159 ns; Loc. = LC_X6_Y6_N6; Fanout = 60; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_12\|key_buffer:comb_42\|state.s2'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.964 ns" { lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.37 % ) " "Info: Total cell delay = 3.375 ns ( 41.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 58.63 % ) " "Info: Total interconnect delay = 4.784 ns ( 58.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.159 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technolo