dpsk.tan.qmsg

来自「用vhdl语言实现2DPSK数字传输」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50MHz " "Info: Assuming node \"clk_50MHz\" is an undefined clock" {  } { { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_50MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}