📄 dpsk.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "34 " "Warning: Found 34 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[1\]\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 62 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[7\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[7\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[6\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[6\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[5\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[5\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[4\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[4\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[3\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[3\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[2\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[2\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[1\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[0\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[0\]\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 62 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low1\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[0\]\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 20 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|bit_alert\[1\] " "Info: Detected gated clock \"DPSK_shell:inst\|LCM_pre:comb_12\|bit_alert\[1\]\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 14 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|bit_alert\[1\]" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|clk_ser " "Info: Detected gated clock \"DPSK_shell:inst\|LCM_pre:comb_12\|clk_ser\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 6 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|clk_ser" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[1\]\" as buffer" { } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 20 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|LCM_pre:comb_12\|wave_low\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qb\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qb\[0\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qb\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qb\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qb\[1\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qb\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qb\[2\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qb\[2\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qb\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|clk_div:comb_5\|Equal1 " "Info: Detected gated clock \"DPSK_shell:inst\|clk_div:comb_5\|Equal1\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 14 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|Equal1" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qc\[2\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qc\[2\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 35 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qc\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qc\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qc\[1\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 35 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qc\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qc\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qc\[0\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 35 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qc\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|clk_div:comb_5\|Equal0~128 " "Info: Detected gated clock \"DPSK_shell:inst\|clk_div:comb_5\|Equal0~128\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|Equal0~128" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|clk_div:comb_5\|Equal0~127 " "Info: Detected gated clock \"DPSK_shell:inst\|clk_div:comb_5\|Equal0~127\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|Equal0~127" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|clk_div:comb_5\|qa\[8\] " "Info: Detected ripple clock \"DPSK_shell:inst\|clk_div:comb_5\|qa\[8\]\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|qa\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|clk_div:comb_5\|Equal0 " "Info: Detected gated clock \"DPSK_shell:inst\|clk_div:comb_5\|Equal0\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|Equal0" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|key_buffer:comb_11\|state.s2 " "Info: Detected ripple clock \"DPSK_shell:inst\|key_buffer:comb_11\|state.s2\" as buffer" { } { { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|key_buffer:comb_11\|state.s2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|pass " "Info: Detected ripple clock \"DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|pass\" as buffer" { } { { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|pass" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|clk_div:comb_5\|Equal2 " "Info: Detected gated clock \"DPSK_shell:inst\|clk_div:comb_5\|Equal2\" as buffer" { } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 15 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|clk_div:comb_5\|Equal2" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|demodulate:comb_10\|q\[0\] " "Info: Detected ripple clock \"DPSK_shell:inst\|demodulate:comb_10\|q\[0\]\" as buffer" { } { { "../Creativity/demodulate.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/demodulate.v" 12 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|demodulate:comb_10\|q\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|demodulate:comb_10\|q\[3\] " "Info: Detected ripple clock \"DPSK_shell:inst\|demodulate:comb_10\|q\[3\]\" as buffer" { } { { "../Creativity/demodulate.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/demodulate.v" 12 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|demodulate:comb_10\|q\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|demodulate:comb_10\|q\[1\] " "Info: Detected ripple clock \"DPSK_shell:inst\|demodulate:comb_10\|q\[1\]\" as buffer" { } { { "../Creativity/demodulate.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/demodulate.v" 12 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|demodulate:comb_10\|q\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DPSK_shell:inst\|demodulate:comb_10\|q\[2\] " "Info: Detected ripple clock \"DPSK_shell:inst\|demodulate:comb_10\|q\[2\]\" as buffer" { } { { "../Creativity/demodulate.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/demodulate.v" 12 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|demodulate:comb_10\|q\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DPSK_shell:inst\|demodulate:comb_10\|Equal0 " "Info: Detected gated clock \"DPSK_shell:inst\|demodulate:comb_10\|Equal0\" as buffer" { } { { "../Creativity/demodulate.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/demodulate.v" 17 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DPSK_shell:inst\|demodulate:comb_10\|Equal0" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcdcont:inst1\|clockdiv:div\|clock_int " "Info: Detected ripple clock \"lcdcont:inst1\|clockdiv:div\|clock_int\" as buffer" { } { { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } } { "d:/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcdcont:inst1\|clockdiv:div\|clock_int" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50MHz register DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\] register DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\] 48.21 MHz 20.743 ns Internal " "Info: Clock \"clk_50MHz\" has Internal fmax of 48.21 MHz between source register \"DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\]\" and destination register \"DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\]\" (period= 20.743 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.372 ns + Longest register register " "Info: + Longest register to register delay is 7.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\] 1 REG LC_X8_Y7_N9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N9; Fanout = 8; REG Node = 'DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } "NODE_NAME" } } { "../Creativity/my_syn_counter.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/my_syn_counter.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.861 ns) + CELL(0.200 ns) 3.061 ns DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|s\[4\] 2 COMB LC_X8_Y10_N0 3 " "Info: 2: + IC(2.861 ns) + CELL(0.200 ns) = 3.061 ns; Loc. = LC_X8_Y10_N0; Fanout = 3; COMB Node = 'DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|s\[4\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] } "NODE_NAME" } } { "../Creativity/phase_counter.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_counter.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.720 ns) + CELL(0.591 ns) 7.372 ns DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\] 3 REG LC_X8_Y6_N9 3 " "Info: 3: + IC(3.720 ns) + CELL(0.591 ns) = 7.372 ns; Loc. = LC_X8_Y6_N9; Fanout = 3; REG Node = 'DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.311 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.791 ns ( 10.73 % ) " "Info: Total cell delay = 0.791 ns ( 10.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.581 ns ( 89.27 % ) " "Info: Total interconnect delay = 6.581 ns ( 89.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.372 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "7.372 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } { 0.000ns 2.861ns 3.720ns } { 0.000ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-12.662 ns - Smallest " "Info: - Smallest clock skew is -12.662 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 13.413 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50MHz\" to destination register is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[8\] 2 REG LC_X7_Y6_N8 2 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X7_Y6_N8; Fanout = 2; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.914 ns) 6.398 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 3 COMB LC_X8_Y6_N0 33 " "Info: 3: + IC(1.289 ns) + CELL(0.914 ns) = 6.398 ns; Loc. = LC_X8_Y6_N0; Fanout = 33; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.203 ns" { DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.097 ns) + CELL(0.918 ns) 13.413 ns DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\] 4 REG LC_X8_Y6_N9 3 " "Info: 4: + IC(6.097 ns) + CELL(0.918 ns) = 13.413 ns; Loc. = LC_X8_Y6_N9; Fanout = 3; REG Node = 'DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\|qout\[7\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.015 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.289 ns ( 31.98 % ) " "Info: Total cell delay = 4.289 ns ( 31.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.124 ns ( 68.02 % ) " "Info: Total interconnect delay = 9.124 ns ( 68.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } { 0.000ns 0.000ns 1.738ns 1.289ns 6.097ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 26.075 ns - Longest register " "Info: - Longest clock path from clock \"clk_50MHz\" to source register is 26.075 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[0\] 2 REG LC_X7_Y6_N0 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X7_Y6_N0; Fanout = 4; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.305 ns) + CELL(0.914 ns) 6.414 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0~127 3 COMB LC_X8_Y6_N7 1 " "Info: 3: + IC(1.305 ns) + CELL(0.914 ns) = 6.414 ns; Loc. = LC_X8_Y6_N7; Fanout = 1; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0~127'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.219 ns" { DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 7.697 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 4 COMB LC_X8_Y6_N0 33 " "Info: 4: + IC(0.772 ns) + CELL(0.511 ns) = 7.697 ns; Loc. = LC_X8_Y6_N0; Fanout = 33; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(17.460 ns) + CELL(0.918 ns) 26.075 ns DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\] 5 REG LC_X8_Y7_N9 8 " "Info: 5: + IC(17.460 ns) + CELL(0.918 ns) = 26.075 ns; Loc. = LC_X8_Y7_N9; Fanout = 8; REG Node = 'DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\|q\[4\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "18.378 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } "NODE_NAME" } } { "../Creativity/my_syn_counter.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/my_syn_counter.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns ( 18.41 % ) " "Info: Total cell delay = 4.800 ns ( 18.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.275 ns ( 81.59 % ) " "Info: Total interconnect delay = 21.275 ns ( 81.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.075 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.075 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 17.460ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } { 0.000ns 0.000ns 1.738ns 1.289ns 6.097ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.075 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.075 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 17.460ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "../Creativity/my_syn_counter.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/my_syn_counter.v" 11 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.372 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "7.372 ns" { DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|s[4] DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } { 0.000ns 2.861ns 3.720ns } { 0.000ns 0.200ns 0.591ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] } { 0.000ns 0.000ns 1.738ns 1.289ns 6.097ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "26.075 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "26.075 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[0] DPSK_shell:inst|clk_div:comb_5|Equal0~127 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] } { 0.000ns 0.000ns 1.738ns 1.305ns 0.772ns 17.460ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.511ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_50MHz 116 " "Warning: Circuit may not operate. Detected 116 non-operational path(s) clocked by clock \"clk_50MHz\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
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