dpsk.fit.rpt

用vhdl语言实现2DPSK数字传输

Fitter report for DPSK
Wed Oct 31 11:32:45 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Control Signals
 14. Global & Other Fast Signals
 15. Non-Global High Fan-Out Signals
 16. Interconnect Usage Summary
 17. LAB Logic Elements
 18. LAB-wide Signals
 19. LAB Signals Sourced
 20. LAB Signals Sourced Out
 21. LAB Distinct Inputs
 22. Fitter Device Options
 23. Advanced Data - General
 24. Advanced Data - Placement Preparation
 25. Advanced Data - Placement
 26. Advanced Data - Routing
 27. Fitter Messages
 28. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Wed Oct 31 11:32:45 2007    ;
; Quartus II Version    ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name         ; DPSK                                     ;
; Top-level Entity Name ; DPSK                                     ;
; Family                ; MAX II                                   ;
; Device                ; EPM1270T144C5                            ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 271 / 1,270 ( 21 % )                     ;
; Total pins            ; 51 / 116 ( 44 % )                        ;
; Total virtual pins    ; 0                                        ;
; UFM blocks            ; 0 / 1 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EPM1270T144C5                  ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;