s_simd.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module S_simd(
							DC_B_Src1,
							DC_B_Src2,
							DC_ADD2,
							DC_SUB2,
							DC_SADD2,
							DC_SADDU4,
							DC_SADDUS2,
							DC_CMPEQ2 ,     //C64
							DC_CMPEQ4 ,     
							DC_CMPGT2 ,      
							DC_CMPGTU4 ,    //
              DC_W_Src2inv,
							S_B_UWrite_Data,
							en_instruction_execute,
							simd_write_reg
							);




input  DC_ADD2, DC_SUB2, DC_SADD2, DC_SADDU4, DC_SADDUS2, DC_CMPEQ2, DC_CMPEQ4, DC_CMPGT2, DC_CMPGTU4 ;
input  en_instruction_execute;
output [31:0]  S_B_UWrite_Data;
output         simd_write_reg;

input         DC_W_Src2inv;
input [31:0]  DC_B_Src1;
input [31:0]  DC_B_Src2;
reg [31:0]    Sat_Result;
reg [31:0]    CMP_Result;

wire        use_result;
wire [31:0] Adder_16_Result;
wire [31:0] Xor_Src1_Src2;
wire				compare;

assign Xor_Src1_Src2=DC_B_Src1^DC_B_Src2;
assign compare= DC_CMPEQ2||DC_CMPEQ4||DC_CMPGT2||DC_CMPGTU4;
assign use_result=(DC_ADD2||DC_SUB2||DC_SADD2||DC_SADDU4||DC_SADDUS2||compare);
assign simd_write_reg=en_instruction_execute&&use_result;



wire Cout_16_high;
wire Cout_16_low;
wire Cout_15_high;
wire Cout_15_low;
wire Cout_8_high;
wire Cout_8_low;
wire [31:0]  S_B_UWrite_Data;

assign      S_B_UWrite_Data=compare?CMP_Result:(DC_SADD2||DC_SADDU4||DC_SADDUS2)?Sat_Result:Adder_16_Result; 





always @(DC_B_Src1  or DC_B_Src2 or en_instruction_execute or Adder_16_Result or Cout_16_high or Cout_16_low 
        or Cout_15_high or Cout_15_low or Cout_8_high or Cout_8_low or DC_SADDU4 or DC_SADD2 or DC_SADDUS2 
        or compare or DC_CMPEQ2 or DC_CMPEQ4 or DC_CMPGT2 or DC_CMPGTU4 or Xor_Src1_Src2)
begin      
  Sat_Result=Adder_16_Result;
  CMP_Result=32'h0;
  
  //for DC_W_SADDU4, if it's cout is 1 then overflow, perform saturation, let it be 2^8-1
  if(DC_SADDU4) begin
      if(Cout_8_low) Sat_Result[7:0]=8'hff;
      else Sat_Result[7:0]=Adder_16_Result[7:0];
      if(Cout_16_low) Sat_Result[15:8]=8'hff;
      else Sat_Result[15:8]=Adder_16_Result[15:8];
      if(Cout_8_high) Sat_Result[23:16]=8'hff;
      else Sat_Result[23:16]=Adder_16_Result[23:16];
      if(Cout_16_high) Sat_Result[31:24]=8'hff;
      else Sat_Result[31:24]=Adder_16_Result[31:24];      
    end
  
   //for DC_W_SADD2
   if(DC_SADD2) begin
      //if src1 and src2 are positive, if msb is 1 then overflow, perform saturation, let it be 2^15-1
      if(~(DC_B_Src1[15]||DC_B_Src2[15])&&Cout_15_low) Sat_Result[15:0]=16'h7fff;
      //if src1 and src2 are negative, if msb is 0 then underflow, perform saturation, let it be -2^15
      if (DC_B_Src1[15]&&DC_B_Src2[15]&&!Cout_15_low) Sat_Result[15:0]=16'h8000;
      
     
      
     //if src1 and src2 are positive, if msb is 1 then overflow, perform saturation, let it be 2^15-1
     if(~(DC_B_Src1[31]||DC_B_Src2[31])&&Cout_15_high) Sat_Result[31:16]=16'h7fff;
      //if src1 and src2 are negative, if cout is 1 and msb is 0 then underflow, perform saturation, let it be -2^15
     if (DC_B_Src1[31]&&DC_B_Src2[31]&&!Cout_15_high) Sat_Result[31:16]=16'h8000;
      
     
      
    end       

    //for DC_W_SADDUS2,
    if(DC_SADDUS2) begin
      //if src2 are negative, if result is negative, then result is 0;
      if(~Cout_15_low&&DC_B_Src2[15]&&~DC_B_Src1[15]) Sat_Result[15:0]=16'h0;
      //if src2 are positive, if cout is 1, then result is 2^16-1
      if(!DC_B_Src2[15]&&DC_B_Src1[15]&&Cout_15_low) Sat_Result[15:0]=16'hffff;
      

      //if src2 are negative, if result is negative, then result is 0;
      if(~Cout_16_high&&DC_B_Src2[31]&&~DC_B_Src1[31]) Sat_Result[31:16]=16'h0;
      //if src2 are positive, if cout is 1, then result is 2^16-1
      if(!DC_B_Src2[31]&&DC_B_Src1[31]&&Cout_15_high) Sat_Result[31:16]=16'hffff;

      end 
 
 //c64 instructions begin
 		if(DC_CMPEQ2) begin

 			if(Xor_Src1_Src2[31:16]==16'hffff) CMP_Result[1]=1;
 			
 			if(Xor_Src1_Src2[15:0]==16'hffff) CMP_Result[0]=1;
 	
 		end 
 		
 		if(DC_CMPEQ4) begin

 		  if(Xor_Src1_Src2[31:24]==8'hff) CMP_Result[3]=1;
 		
 		  if(Xor_Src1_Src2[23:16]==8'hff) CMP_Result[2]=1;
 		
 		  if(Xor_Src1_Src2[15:8]==8'hff) CMP_Result[1]=1;
 	
 	    if(Xor_Src1_Src2[7:0]==8'hff) CMP_Result[0]=1;
 	    
 	  end
 	    
 		if(DC_CMPGT2) begin

    if (!DC_B_Src1[31]&&!DC_B_Src2[31]) 	CMP_Result[1]=1;  
    if (Xor_Src1_Src2[31]&&!(Xor_Src1_Src2[31:16]==16'hffff)&&Cout_15_high)   CMP_Result[1]=1;

 		
          if (!DC_B_Src1[15]&&!DC_B_Src2[15]) 	CMP_Result[0]=1;  
 	  if (Xor_Src1_Src2[15]&&!(Xor_Src1_Src2[15:0]==16'hffff)&&Cout_15_low) 	CMP_Result[0]=1;

 		end
 		
 		if(DC_CMPGTU4) begin

 			if(Cout_16_high&&(~(Xor_Src1_Src2[31:24]==8'hff)))CMP_Result[3]=1;
 			
 			if(Cout_8_high&&(~(Xor_Src1_Src2[23:16]==8'hff)))CMP_Result[2]=1;
 			
 			if(Cout_16_low&&(~(Xor_Src1_Src2[15:8]==8'hff))) CMP_Result[1]=1;
 		
 			if(Cout_8_low&&(~(Xor_Src1_Src2[7:0]==8'hff)))  CMP_Result[0]=1;
 		end
 
 
 
  end          

wire simd_8;
assign simd_8=~(DC_SADDU4||DC_CMPEQ4||DC_CMPGTU4);
wire compare_8;
assign compare_8=DC_CMPEQ4||DC_CMPGTU4;
  
simd_adder16  adder_high_16(
                            .Src1  (DC_B_Src1[31:16]),
                            .Src2  (DC_B_Src2[31:16]),
                            .cout_in  (DC_W_Src2inv),
                            .simd_8(simd_8),
                            .compare_8(compare_8),
                            .sum  (Adder_16_Result[31:16]),
                            .Cout16 (Cout_16_high),
                            .Cout15 (Cout_15_high),
                            .Cout8  (Cout_8_high)
                            );     
                            
simd_adder16  adder_low_16(
                            .Src1  (DC_B_Src1[15:0]),
                            .Src2  (DC_B_Src2[15:0]),
                            .cout_in  (DC_W_Src2inv),
                            .simd_8(simd_8),
                            .compare_8(compare_8),
                            .sum  (Adder_16_Result[15:0]),
                            .Cout16 (Cout_16_low),
                            .Cout15 (Cout_15_low),
                            .Cout8  (Cout_8_low)
                            );
        
endmodule