s_left_shifter.v

来自「verilog, TMSC6415 S单元代码」· Verilog 代码 · 共 15 行

`timescale 1ns/10ps

module S_Left_Shifter(
src,
count,
result
);

input [39:0]  src;
input [5:0]   count;
output [39:0] result;

assign result=src<<count;

endmodule