s_adder_32.v

来自「verilog, TMSC6415 S单元代码」· Verilog 代码 · 共 14 行

`resetall
`timescale 1ns/10ps

module S_Adder_32(A, B ,Cin, D, Cout);
input  [31:0] A;
input  [31:0] B;
input         Cin;
output [31:0] D;
output        Cout;

assign {Cout,D}=A+B+Cin;

endmodule