s_adder_8.v

来自「verilog, TMSC6415 S单元代码」· Verilog 代码 · 共 16 行

`resetall
`timescale 1ns/10ps

module S_Adder_8(A, B ,C, D, Cout);
input  [7:0] A;
input  [7:0] B;
input         C;
output [7:0] D;
output        Cout;

wire    [7:0] D;
wire          Cout;

assign {Cout, D}=A+B+C;

endmodule