s_upack.v

来自「verilog, TMSC6415 S单元代码」· Verilog 代码 · 共 37 行

module S_UPACK(DC_B_Src1,  DC_B_Src2,  
  DC_W_PACKH2,  DC_W_PACKHL2,  DC_W_PACKLH2,
DC_W_UNPKHU4,  DC_W_UNPKLU4 ,S_UPACK_out);

    input [31:0] DC_B_Src1;
    input [31:0] DC_B_Src2;
  //  input  DC_W_PACK2;
    input DC_W_PACKH2;
    input DC_W_PACKHL2;
    input DC_W_PACKLH2;
     input DC_W_UNPKHU4;
     input DC_W_UNPKLU4;
   //  input DC_MVC;
    output [31:0] S_UPACK_out;
     reg [31:0]  S_UPACK_out;
always @( DC_B_Src1 or DC_B_Src2 
 or DC_W_PACKH2 or DC_W_PACKHL2 or DC_W_PACKLH2
or	DC_W_UNPKHU4  or	DC_W_UNPKLU4 )
   begin
       S_UPACK_out=32'h0;
       //if(DC_MVC)
          //S_UPACK_out=DC_B_Src2;
      // if(DC_W_PACK2)
          // S_UPACK_out={DC_B_Src1[15:0],DC_B_Src2[15:0]};
        if(DC_W_PACKH2)
             S_UPACK_out={DC_B_Src1[31:16],DC_B_Src2[31:16]};
        if(DC_W_PACKHL2)
               S_UPACK_out={DC_B_Src1[31:16],DC_B_Src2[15:0]};
         if(DC_W_PACKLH2)
               S_UPACK_out={DC_B_Src1[15:0],DC_B_Src2[31:16]};
          if(DC_W_UNPKHU4)
               S_UPACK_out={8'h0,DC_B_Src2[31:24],8'h0,DC_B_Src2[23:16]};
           if(DC_W_UNPKLU4)
                   S_UPACK_out={8'h0,DC_B_Src2[15:8],8'h0,DC_B_Src2[7:0]};
     end
endmodule