dc_s_decode.v

verilog, TMSC6415 S单元代码

      I_DC_W_SUB=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //src1(sint)   
        I_DC_W_Ssrc1re=1'b1;
      else
        //src1(scst)
        Src1_signed=1'b0;        //wjh modify it ,because it is scst
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end

    6'b010001: //SUB2 instruction            
    begin
      I_DC_W_Src2inv=1'b1;
      I_DC_W_SUB2=1'b1;
      I_DC_W_Ssrc1re=1'b1;   //wjh added
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end

    6'b001011, //XOR instruction
    6'b001010: //XOR instruction
    begin
      I_DC_W_XOR=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //src1(sint)   
        I_DC_W_Ssrc1re=1'b1;
      else
        //src1(scst)
        Src1_signed=1'b0;  //wjh modify it ,because it is scst
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end
		
		6'b011101:  				// CMPEQ2   instruction    
		begin
		I_DC_W_Src2inv=1'b1; 
		I_DC_W_CMPEQ2=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;     

		end
		
		
		6'b011100:  				// CMPEQ4   instruction    
		begin 
		I_DC_W_Src2inv=1'b1;
		I_DC_W_CMPEQ4=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1; 
		end
		
		6'b010100:  				// CMPGT2   instruction    
		begin
		I_DC_W_Src2inv=1'b1; 
		I_DC_W_CMPGT2=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1; 
		
		end
		
		6'b010101:  				// CMPGTU4   instruction    
		begin 
		I_DC_W_Src2inv=1'b1;
		I_DC_W_CMPGTU4=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		I_DC_W_U=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1; 
		
		end
		
		6'b001001:  				// PACKH2   instruction    
		begin 
		I_DC_W_PACKH2=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;
		
		end
		
		
		6'b001000:  				// PACKHL2   instruction    
		begin 
		I_DC_W_PACKHL2=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;
		end
		
		
		6'b010000:  				// PACKLH2   instruction    
		begin
		I_DC_W_PACKLH2=1'b1;
		I_DC_W_Ssrc1re=1'b1;
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;
		end
		
		
		6'b011000,  			//  SHR2_C  	    instruction    
		6'b011001:  			//  SHRU2_C 	    instruction   
		begin 
		
		/* if(DP_B_Sfield[0]==1'b1) begin
			I_DC_W_U=1'b1;
			I_DC_W_SHR2=1'b1;
			end else
			I_DC_W_SHRU2=1'b1;*/                     

		if(DP_B_Sfield[0]==1'b0) begin  
		  I_DC_W_U=1'b0;                
			I_DC_W_SHR2=1'b1;             
			end else
			begin                      
			I_DC_W_U=1'b1;                
         I_DC_W_SHRU2=1'b1; 
       end           
		if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;
		end
		
		
    /*6'b001101:  				// BNOP_Reg   instruction    
    begin 
    I_DC_W_BNOP_Reg=1'b1;
    I_S_UBranch_Inst=1'b1;
    if(DP_B_Sfield[6]==1'b1)
          I_I_DC_W_TriCrossRE=1'b1;
        else
          I_DC_W_Ssrc2re=1'b1;
    end*/
    
 		6'b111100:					// UNPKHU4 & UNPKLU4
 		begin
    if(DP_B_Sfield[6]==1'b1)   
  		I_I_DC_W_TriCrossRE=1'b1;
			else                       
  		I_DC_W_Ssrc2re=1'b1;
  		
    if (DP_B_Sfield[11:7]==5'b00011)
    	I_DC_W_UNPKHU4=1'b1;
    if (DP_B_Sfield[11:7]==5'b00010)
    	I_DC_W_UNPKLU4=1'b1;
    end
    
    
    
    default:
    begin
      //there have not the default selection
    end
    
    endcase
    
    case(DP_B_Sfield[6:0])
    
    7'b0000101:			//ADDKPC     instruction    
    begin
    I_DC_W_ADDKPC=1'b1;
    
    
    end
    
    7'b1000000:			//BDEC       instruction    
    begin 
    I_DC_W_BDEC=1'b1;
   // Dst_use=1'b1;
  	 I_DC_W_Ssrc2re=1'b1;
//  	 I_S_UBranch_Inst=1'b1;// 10.8

    end
    
    7'b0000000:			//BPOS       instruction    
    begin 
    I_DC_W_BPOS=1'b1;
   // Dst_use=1'b1;
    I_DC_W_Ssrc2re=1'b1;
//    I_S_UBranch_Inst=1'b1;// 10.8

    end
    
    7'b0000100:			//BNOP_Cst   instruction    
    begin 
    I_DC_W_BNOP_Cst=1'b1;
//    I_S_UBranch_Inst=1'b1;// 10.8

    
    end
    
    
    
    
    default:
    begin
      //there have not the default selection
    end
    
    endcase
    
  end
  
  if(DP_B_Smode[2:0]==3'b001)
  begin
    //this is only for ADDK instruction
    I_DC_W_ADD=1'b1;
    I_DC_W_U=1'b1;
    //use the Dst addr for src2 data
  //  Dst_use=1'b1;
    Src1_signed=1'b0;
    I_DC_W_Ssrc2re=1'b1;  //wjh added
  end

  if(DP_B_Smode[2:0]==3'b010)
  begin
    //the src1 data come from the ucsta ucstb
    //src1(ucsta,ucstb) src2 dst
    Src1_ustab=1'b1;
    I_DC_W_Ssrc2re=1'b1;
    if(DP_B_Sfield[1:0]==2'b11)
      I_DC_W_CLR=1'b1;
    if(DP_B_Sfield[1:0]==2'b10)
      I_DC_W_SET=1'b1;
    if(DP_B_Sfield[1:0]==2'b01)
      I_DC_W_EXT=1'b1;
    if(DP_B_Sfield[1:0]==2'b00)
    begin
      I_DC_W_EXT=1'b1;    //wjh modify it, it should be EXT
      I_DC_W_U=1'b1;
    end
  end

  if(DP_B_Smode[2:0]==3'b011)
  begin
    //just used for MVK and MVKH instruction
    if(DP_B_Sfield[0]==1'b0) begin
      I_DC_W_MVK=1'b1;
      Src1_signed=1'b0;  //wjh added
    end else begin
      I_DC_W_Ssrc2re=1'b1;
    //  Dst_use=1'b1;
      Src1_signed=1'b1;
      I_DC_W_MVKH=1'b1;
    end
  end

  if(DP_B_Smode[2:0]==3'b100)
  begin
    //just for Bcst
    I_DC_W_BCst=1'b1;
//    I_S_UBranch_Inst= 1'b1 ;
    //1: used 0: not used
    //indicate the PCE1 will be used or not
    PCE1_use=1'b1;
  end
  
  //2003-10-9, wjh add for c64 extension
  if(DP_B_Smode[2:0]==3'b101)
  begin
    case (DP_B_Sfield[3:0])
       
    4'b0000: 								//SADD2
    begin
      I_DC_W_SADD2=1'b1;
      I_DC_W_Ssrc1re=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end    
    4'b0001: 									//		SADDUS2
    begin
      I_DC_W_SADDUS2=1'b1;
      I_DC_W_Ssrc1re=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end       
    4'b0011: 	//		SADDU4
    begin
      I_DC_W_SADDU4=1'b1;
      I_DC_W_Ssrc1re=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end 
    4'b0101:  //    SUB C64 add  10.22 gongxiao
    begin
        //I_DC_W_Src2inv=1'b1;
        I_SUB_RE=1'b1;
        I_DC_W_SUB=1'b1;
        I_DC_W_Ssrc1re=1'b1;
      //if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      //else
       // I_DC_W_Ssrc2re=1'b1;  gongxiao 08.1.16 SBU新增情况只能读交叉通路
    end
    4'b0110:   //ANDN       
    begin  
    I_DC_W_ANDN=1'b1;
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    
    4'b1111:   //PACK2      
    begin 
    I_DC_W_PACK2=1'b1; 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    4'b1001:   //SHLMB      
    begin  
    I_DC_W_SHLMB=1'b1; 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    4'b0111,   //SHR2   
    4'b1000:   //SHRU2     
    begin 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1; 
     /*if(DP_B_Sfield[0]==1'b0) begin
			I_DC_W_U=1'b1;
			I_DC_W_SHR2=1'b1;
			end else
			I_DC_W_SHRU2=1'b1;
     */
    if(DP_B_Sfield[0]==1'b1) begin
			I_DC_W_U=1'b0;
			I_DC_W_SHR2=1'b1;
			end else
			begin
			I_DC_W_U=1'b1;
			I_DC_W_SHRU2=1'b1;
         end
    end
    
    4'b1010:   //SHRMB      
    begin  
    I_DC_W_SHRMB=1'b1; 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
         
    
    4'b0010:   //SPACK2     
    begin  
    I_DC_W_SPACK2=1'b1; 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    4'b0100:   //SPACKU4    
    begin  
    I_DC_W_SPACKU4=1'b1; 
    I_DC_W_Ssrc1re=1'b1;
    if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
    else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    default: 
    begin
      //nothing
    end   
    
    endcase
  end
end


/////////////////////////////////////////////////////////////////
// ztz modify the decode to  I_S_UBranch_Inst signal
always@(DP_B_Sfield or DP_B_Smode or DP_W_SBDECBPOS) 
begin
       I_S_UBranch_Inst=1'b0 ; 
   if((DP_B_Smode==3'b000)&&(DP_B_Sfield[5:0]==6'b001101))
       I_S_UBranch_Inst=1'b1 ;
   if((DP_B_Smode==3'b000)&&(DP_B_Sfield[5:0]==6'b000011))
       I_S_UBranch_Inst=1'b1 ;
   if(DP_W_SBDECBPOS)
       I_S_UBranch_Inst=1'b1 ;
   if((DP_B_Smode==3'b000)&&(DP_B_Sfield[6:0]==7'b0000100))     
       I_S_UBranch_Inst=1'b1 ; 
   if(DP_B_Smode==3'b100)
       I_S_UBranch_Inst=1'b1 ;  
 end
    
 /////////////////////////////////////////////////////////////////////// 
 
  
assign DC_B_Ssrc1addr[4:0]=DP_B_Sfield[11:7];

assign DC_B_Ssrc2addr[4:0]=Dst_use?DP_B_Sfield[21:17]:DP_B_Sfield[16:12];
assign I_DC_B_Dst_Address[4:0]=DP_B_Sfield[21:17];

assign I_DC_B_TriCrossAddr[4:0]=DP_B_Sfield[16:12];


assign I_DC_B_TriSTaddr[4:0]={DP_B_Sfield[16:13],1'b1};//high 8 bit addr




//hcm modified 2003-12-10.
always@(I_DC_W_MVK or I_DC_W_MVKH or I_DC_W_ADD or I_DC_W_U or PCE1_use or Src1_ustab
        or Src1_signed or DP_B_Sfield or I_DC_W_Ssrc1re or  I_DC_W_ADDKPC or I_DC_W_BDEC 
        or I_DC_W_BPOS or I_DC_W_BNOP_Cst or DP_PCE1)
begin
    I_DC_B_Src1[31:0]={{28{(~Src1_signed)& DP_B_Sfield[11]}},DP_B_Sfield[11:7]};
  
  if(I_DC_W_MVK | I_DC_W_MVKH | I_DC_W_ADD & I_DC_W_U)
    I_DC_B_Src1[31:0]={{16{~Src1_signed & DP_B_Sfield[16]}},DP_B_Sfield[16:1]};
  if(PCE1_use)
     
    //Prepare Src for Bcst
     I_DC_B_Src1[31:0]={{9{DP_B_Sfield[21]}},DP_B_Sfield[21:1],2'b0};  //MODIFY BY DZJ
  if (I_DC_W_ADDKPC)		I_DC_B_Src1[31:0]={{23{DP_B_Sfield[16]}},DP_B_Sfield[16:10],2'b0};
  
  
  if(Src1_ustab)
    I_DC_B_Src1[31:0]={{22{1'b0}},DP_B_Sfield[11:2]};
    
  if(I_DC_W_BDEC||I_DC_W_BPOS) 
   	I_DC_B_Src1[31:0]={DP_PCE1[31:5],5'b0};//0917
    //  I_DC_B_Src2[31:0]=32'b1;
  if(I_DC_W_BNOP_Cst)
  	I_DC_B_Src1[31:0]={{18{DP_B_Sfield[21]}},DP_B_Sfield[21:10],2'b0}; //src2 18{}
end




//hcm modified 2003-12-10.
always@(PCE1_use or I_DC_W_MVC or I_DC_W_BReg or I_DC_W_Src2_Type 
        or  DP_PCE1 or DP_B_Sfield or I_DC_W_ADDKPC or I_DC_W_BNOP_Cst)
begin
    I_DC_B_Src2[31:0]=32'b0;
  
  if(PCE1_use||I_DC_W_ADDKPC||I_DC_W_BNOP_Cst)
    
    //Prepare Src for Bcst 
    I_DC_B_Src2[31:0]={DP_PCE1[31:5],5'b0};   //MODIFY BY DZJ
  if((I_DC_W_MVC||I_DC_W_BReg)&&I_DC_W_Src2_Type)
    I_DC_B_Src2[31:0]={27'b0,DP_B_Sfield[16:12]};
   
end



assign I_Cst_BDEC [31:0]=(I_DC_W_BDEC||I_DC_W_BPOS)?{{20{DP_B_Sfield[16]}},DP_B_Sfield[16:7],2'h0}:32'h00;

assign I_SSHL_SHL=I_DC_W_SSHL||I_DC_W_SHL;
//assign I_SSHL_EXT=I_DC_W_SSHL||I_DC_W_EXT;
assign   I_SHR_SSHL=I_DC_W_SHR||I_DC_W_SSHL;
assign I_SSHL_SHL_EXT=I_DC_W_SSHL||I_DC_W_SHL||I_DC_W_EXT;
assign I_SSHL_SHL_Src2Type=(I_DC_W_SSHL||I_DC_W_SHL)&&I_DC_W_Src2_Type;
assign  I_SHR_Src2Type=I_DC_W_SHR&&I_DC_W_Src2_Type;
assign  I_SHR_Src2Type_U=I_DC_W_SHR&&!I_DC_W_Src2_Type&&!I_DC_W_U;
assign  I_EXT_DC_U=I_DC_W_EXT&&!I_DC_W_U;
assign  I_log_reg=(I_DC_W_SHL||I_DC_W_SHR)&&I_DC_W_Src2_Type||(I_DC_W_SHL&&I_DC_W_U);
assign  I_use_result=(I_DC_W_CLR||I_DC_W_EXT||I_DC_W_SET||I_DC_W_SHL||I_DC_W_SHR||I_DC_W_SSHL);

assign  I_logic_use_result=(I_DC_W_AND||I_DC_W_MVK||I_DC_W_MVKH||I_DC_W_OR||I_DC_W_XOR||I_DC_W_PACKH2||      
								I_DC_W_PACKHL2 ||      
								I_DC_W_PACKLH2 || 
                I_DC_W_UNPKHU4 ||                            
								I_DC_W_UNPKLU4 ||
								I_DC_W_ANDN    ||
								I_DC_W_PACK2   ||
								I_DC_W_SHLMB   ||
								I_DC_W_SHRMB   ||
								I_DC_W_SPACK2  ||
								I_DC_W_SPACKU4);


endmodule