dc_s_decode.v

verilog, TMSC6415 S单元代码

      DC_W_Z<=I_DC_W_Z;
      SSHL_SHL<=I_SSHL_SHL; //11.19 add        
     //SSHL_EXT<=I_SSHL_EXT; //11.19 add        
     SSHL_SHL_EXT<=I_SSHL_SHL_EXT; //11.19 add    
     SSHL_SHL_Src2Type<=I_SSHL_SHL_Src2Type;//11.19 add
     
     SHR_Src2Type_U<=I_SHR_Src2Type_U;//11.20 add
     SHR_SSHL<=I_SHR_SSHL;
     SHR_Src2Type<=I_SHR_Src2Type;//11.20 add
     EXT_DC_U<=I_EXT_DC_U;//11.20 add
     log_reg<=I_log_reg;
     use_result<=I_use_result;
     logic_use_result<=I_logic_use_result; //08.1.15
      DC_W_Src2inv<=I_DC_W_Src2inv;
      SUB_RE<=I_SUB_RE;
      DC_W_Sinvalid<=I_DC_W_Sinvalid;   
    //  S_UBranch_Inst<= I_S_UBranch_Inst;
    end
  end
end
always @(posedge clk)
begin
   
  if(stall!=1'b1)
  //not Dcache miss and Icache miss
  begin
    DC_W_Src2_Type<=I_DC_W_Src2_Type;
    DC_B_Dst_Address<=I_DC_B_Dst_Address;
    DC_B_Scondaddr[2:0]<=I_DC_B_Scondaddr[2:0];
    
     DC_B_Src1[31:0]<=I_DC_B_Src1[31:0];
    DC_B_Src2[31:0]<=I_DC_B_Src2[31:0];
    Cst_BDEC[31:0]<=I_Cst_BDEC [31:0];
  end
end
reg           src1_re; 
reg           src2_re;
reg           src2_cross;
reg           pre_DC_W_TriSTre;

 

always@(DP_B_Sfield[0] or DP_B_Sfield[3] or DP_B_Sfield[4] or DP_B_Smode or  DP_B_Sfield[5] or DP_W_Sactive)
begin
         src1_re=1'b0;  
   if(~(DP_B_Smode[1] || DP_B_Smode[0] || !DP_B_Sfield[0]))  begin
        src1_re=DP_W_Sactive; 
      end  
   if(!DP_B_Smode[1]  &&( DP_B_Sfield[3] || DP_B_Sfield[4]||  DP_B_Sfield[5])) 
   // mode000在field[0]=0情况下读源1的例外分析。按照这种译码方案会在mode001的ADDK和mode100的BCst产生无效读源1请求
   //当处于mode101时，这部分的判断可能会和下面的if语句条件重合，但这并不会对结果产生影响。因为mode101一定要读源1。
        src1_re=DP_W_Sactive;
        
   if(DP_B_Smode[2] && DP_B_Smode[0]) 
        src1_re=DP_W_Sactive;
            

end     

always@(DP_B_Smode or DP_B_Sfield[1:0] or DP_B_Sfield[6] or DP_B_Sfield[4:3] or DP_W_SBDECBPOS or DP_W_Sactive)
begin

    
 case (DP_B_Smode)
 3'b000:                             //处理mode 000情况还需要进一步分析:部分指令不读源2，但我们不能确定其field[6]是否为0
     if(DP_B_Sfield[6]==1'b0|| DP_W_SBDECBPOS)   begin     //这样在粗译码的情况下可能会产生无效的读交叉通路使能。这种情况是必须要避免的。即使读src2
        src2_re   =DP_W_Sactive ;               //部分指令也不读交叉通路，并且也不能确定field[6]是否为0.对于这些情况我们必须区分出来
        src2_cross=1'b0; 
     end else begin                            //else if (!DP_W_SBDECBPOS)
        src2_cross=DP_W_Sactive;             //
        src2_re   =1'b0; 
     end
 3'b001: begin
         src2_re=DP_W_Sactive ;            //采用这种写法是为了避免综合出锁存器
         src2_cross=1'b0; 
         end
         
 3'b010: begin
         src2_re=DP_W_Sactive ;
         src2_cross=1'b0; 
         end
 3'b011: begin  
           src2_cross=1'b0;  
         if(DP_B_Sfield[0]==1'b1)  
           src2_re=DP_W_Sactive ;
         else              
           src2_re=1'b0 ; 
         end
 3'b101:
     if(DP_B_Sfield[6]==1'b0)  begin
        src2_re   =DP_W_Sactive ;
        src2_cross=1'b0; 
     end else begin 
        src2_cross=DP_W_Sactive;
        src2_re=1'b0;
     end
  default :begin  
         src2_re=1'b0;
         src2_cross=1'b0; 
  end 
  endcase
  
end
   
always@( DP_B_Sfield[5] or DP_B_Sfield[3] or DP_B_Sfield[1] or DP_B_Smode[0] or DP_W_Sactive)  
begin  
    if(DP_B_Sfield[5] && !DP_B_Sfield[3] && !DP_B_Sfield[1] && !DP_B_Smode[0])  
      pre_DC_W_TriSTre=DP_W_Sactive;
    else
      pre_DC_W_TriSTre=1'b0;
 end
 
assign I_DC_W_Sinvalid=DP_W_Sactive;   

assign DC_W_Ssrc1re=  src1_re;                       //粗译码得到的读使能信号
assign DC_W_Ssrc2re=  src2_re;                       //按照当前想法，该信号最先发送到RF
assign I_DC_W_TriCrossRE= src2_cross;
assign I_DC_W_TriSTre= pre_DC_W_TriSTre;
                 
wire          DC_W_Ssrc1re_1;
wire          DC_W_Ssrc2re_1;
wire          I_DC_W_TriCrossRE_1;
wire          I_DC_W_TriSTre_1;

assign DC_W_Ssrc1re_1=DP_W_Sactive & I_DC_W_Ssrc1re;             //精确译码得到的读使能信号
assign DC_W_Ssrc2re_1=DP_W_Sactive & I_DC_W_Ssrc2re;             //这个信号是用来锁存在下一站。是否要将其发送到RF，还需要量化地分析信号产生时机问题。
assign I_DC_W_TriCrossRE_1=DP_W_Sactive & I_I_DC_W_TriCrossRE;   // 这个交叉通路读使能是冗余的信号，因为粗译码的对应该信号也是精确信号。
assign I_DC_W_TriSTre_1=DP_W_Sactive & I_I_DC_W_TriSTre;

assign S_UBranch_Inst= DP_W_Sactive & I_S_UBranch_Inst ;

/*always@(DP_W_SBDECBPOS or DP_B_Smode or DP_B_Sfield[0])
begin
    case(DP_B_Smode) 
    3'b000:  if(DP_W_SBDECBPOS) 
                  Dst_use=1'b1;        //必须将下面的dst-use删除掉
             else Dst_use=1'b0;
    3'b001:       Dst_use=1'b1;
    3'b011:  if(DP_B_Sfield[0])
                  Dst_use=1'b1;
             else Dst_use=1'b0;
   default:       Dst_use=1'b0;
   endcase
                  
end
*/

assign  Dst_use = (DP_udst_Sfield !=3'b000)? 1:0 ;



always @(posedge clk)                    //锁存使能信号输出到E1站，用于操作数选择
begin

  if(stall!=1'b1)
  begin
     Ssrc1re<=DC_W_Ssrc1re_1;
     Ssrc2re<=DC_W_Ssrc2re_1;
     DC_W_TriCrossRE<=I_DC_W_TriCrossRE_1;
     DC_W_TriSTre<=I_DC_W_TriSTre_1;
  end
  end 



always @(DP_B_Sfield or DP_B_Smode or DP_W_Sactive or PDC_con_Value or DC_W_S_SWBP)
begin
  I_DC_W_U=1'b0;
  I_DC_W_SUB2=1'b0;
  I_DC_W_SUB=1'b0;
  I_DC_W_SSHL=1'b0;
  I_DC_W_SHR=1'b0;
  I_DC_W_SHL=1'b0;
  I_DC_W_SET=1'b0;
  I_DC_W_BReg=1'b0;
  I_DC_W_OR=1'b0;
  I_DC_W_MVKH=1'b0;
  I_DC_W_MVC=1'b0;
  I_DC_W_EXT=1'b0;
  I_DC_W_MVK=1'b0;
  I_DC_W_CLR=1'b0;
  I_DC_W_BCst=1'b0;
  I_DC_W_AND=1'b0;
  I_DC_W_ADD2=1'b0;
  I_DC_W_ADD=1'b0;
  I_DC_W_SADD2  =1'b0;
  I_DC_W_SADD  =1'b0;
  
  I_DC_W_SADDU4 =1'b0;
  I_DC_W_SADDUS2=1'b0; 

	I_DC_W_ADDKPC=1'b0;    
  I_DC_W_BDEC=1'b0;      
  I_DC_W_BPOS=1'b0;      
  I_DC_W_BNOP_Cst=1'b0;  
  I_DC_W_CMPEQ2=1'b0;    
  I_DC_W_CMPEQ4=1'b0;    
  I_DC_W_CMPGT2=1'b0;    
  I_DC_W_CMPGTU4=1'b0;   
  I_DC_W_PACKH2=1'b0;    
  I_DC_W_PACKHL2=1'b0;   
  I_DC_W_PACKLH2=1'b0;   
  //I_DC_W_BNOP_Reg=1'b0;  
  I_DC_W_UNPKHU4=1'b0;   
  I_DC_W_UNPKLU4=1'b0;   
  I_DC_W_ANDN=1'b0;      
  I_DC_W_PACK2=1'b0;     
  I_DC_W_SHLMB=1'b0;     
  I_DC_W_SHRMB=1'b0;     
  I_DC_W_SPACK2=1'b0;    
  I_DC_W_SPACKU4=1'b0;   
  I_DC_W_SHR2=1'b0;        
  I_DC_W_SHRU2=1'b0;       


  I_DC_W_Src2_Type=1'b0;
  I_DC_W_Ssrc1re=1'b0;
  I_DC_W_Ssrc2re=1'b0;
  I_I_DC_W_TriSTre=1'b0;
  I_I_DC_W_TriCrossRE=1'b0;
  I_DC_W_XOR=1'b0;
  I_DC_W_Condition_Exec=1'b1;
  I_DC_W_Scondre=1'b1;
  Src1_signed=1'b0;
  
 // Dst_use=1'b0;
  I_SUB_RE=1'b0;
  Src1_ustab=1'b0;
  PCE1_use=1'b0;
//  I_S_UBranch_Inst=1'b0; // 10.8
  I_DC_W_Src2inv=1'b0; //10.27 gongxiao add
  
  if (DC_W_S_SWBP == 1'b1)begin
      case(PDC_con_Value[3:1])  //当条件寄存器信号使能，则在此进行译码选择某一个条件寄存器，同时把条件寄存器地址送出去
      3'b001:
        //use B0 for condition reg
        I_DC_B_Scondaddr=3'b001;
        
      3'b010:
        //use B1 for condition reg
        I_DC_B_Scondaddr=3'b010;
        
      3'b011:
        //use B2 for condition reg
        I_DC_B_Scondaddr=3'b011;
        
      3'b100:
        //use A1 for condition reg
        I_DC_B_Scondaddr=3'b100;
     
      3'b101:
        //use A2 for condition reg
        I_DC_B_Scondaddr=3'b101;
     3'b110:
        //use A0 for condition reg
        I_DC_B_Scondaddr=3'b110;
     
      default:
      //in this path the instruction is unconditional 
      begin
        I_DC_B_Scondaddr=3'b000;
        I_DC_W_Condition_Exec=1'b0;
        I_DC_W_Scondre=1'b0;
      end  
      endcase
  end
  else begin      
      case(DP_B_Sfield[25:23])
      3'b001:
        //use B0 for condition reg
        I_DC_B_Scondaddr=3'b001;
        
      3'b010:
        //use B1 for condition reg
        I_DC_B_Scondaddr=3'b010;
        
      3'b011:
        //use B2 for condition reg
        I_DC_B_Scondaddr=3'b011;
        
      3'b100:
        //use A1 for condition reg
        I_DC_B_Scondaddr=3'b100;
     
      3'b101:
        //use A2 for condition reg
        I_DC_B_Scondaddr=3'b101;
     3'b110:
        //use A0 for condition reg
        I_DC_B_Scondaddr=3'b110;
      default:
      //in this path the instruction is unconditional 
      begin
        I_DC_B_Scondaddr=3'b000;
        I_DC_W_Condition_Exec=1'b0;
        I_DC_W_Scondre=1'b0;
      end  
      endcase
   end

  if(DP_B_Smode[2:0]==3'b000)
  begin
    //the basic mode (src1  src2  dst)
    case(DP_B_Sfield[5:0])
    6'b000111, //ADD instruction
    6'b000110: //ADD instruction
    begin
      //ADD instruction
      I_DC_W_ADD=1'b1;
      if(DP_B_Sfield[0]==1'b1)
      //ADD  src1(sint)  src2(xsint)  dst(sint)
        I_DC_W_Ssrc1re=1'b1;
      //ADD  src1(cst)  src2(xsint)  dst(sint)
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end
    
    6'b000001: //ADD2 instruction
    begin
      //ADD2 instruction
      I_DC_W_ADD2=1'b1;
      I_DC_W_Ssrc1re=1'b1;
      //ADD2  src1(sint)  src2(xsint)  dst(sint)
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end

    6'b011111, //AND instruction
    6'b011110: //AND instruction
    begin
      //AND instruction
      I_DC_W_AND=1'b1;
//    I_DC_W_Ssrc1re=1'b1;  //wjh delete it  generate cst
      if(DP_B_Sfield[0]==1'b1)
        //AND  src1(scst)  src2(xsint)  dst(sint)
        I_DC_W_Ssrc1re=1'b1;
        //AND  src1(sint)  src2(xsint)  dst(sint)
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end

    6'b001101, //B reg   BNOP_reg译码一样，合并 08.1.15
    6'b000011: //B creg  B IRP 和 B NRP
    begin
      I_DC_W_BReg=1'b1;
 //     I_S_UBranch_Inst=1'b1;// 10.8
      if(DP_B_Sfield[1]==1'b1)// B creg
        //B  src1(null)  src2(creg)  dst(null)
        //the creg read operation is performed in 
        //E1 stage, the address of creg is transited 
        //through the source 2 data
        I_DC_W_Src2_Type=1'b1; 
      else                     //B reg
      //B  src1(null)  src2(xuint)  dst(null)
      //the common reg is read in DC stage
      begin
        if(DP_B_Sfield[6]==1'b1)
          I_I_DC_W_TriCrossRE=1'b1;
        else
          I_DC_W_Ssrc2re=1'b1;      
      end
    end
    6'b100000: //SADD  instruction  10.23 gongxiao add
    begin
       I_DC_W_SADD=1'b1;
      I_DC_W_Ssrc1re=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end 
    
    6'b111111, //CLR instruction
    6'b101111, //EXT instruction
    6'b111011, //SET instruction
    6'b101011: //EXTU instruction 
    begin
      if(DP_B_Sfield[4]==1'b1)
      begin
        if(DP_B_Sfield[2]==1'b1)
          //CLR  src1(ucsta,ucstb)  src2(xuint)  dst(uint)
          I_DC_W_CLR=1'b1;
        else
          //SET  src1(ucsta,ucstb)  src2(xuint)  dst(uint)
          I_DC_W_SET=1'b1;
      end
      else
      begin
        //EXT  src1(ucsta,ucstb)  src2(xsint)  dst(sint) 
        I_DC_W_EXT=1'b1;
        if(DP_B_Sfield[2]==1'b0)
          //EXTU  src1(ucsta,ucstb)  src2(xuint)  dst(uint)          
          I_DC_W_U=1'b1;
      end
      I_DC_W_Ssrc1re=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;      
    end      
 
    6'b001111, //MVC instruction MV creg to dreg
    6'b001110: //MVC instruction MV dreg to creg
    begin
      I_DC_W_MVC=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //MVC  src1(null) src2(creg)  dst(dreg)          
        I_DC_W_Src2_Type=1'b1;
      else
      begin
        //MVC  src1(null) src2(dreg)  dst(creg)          
        if(DP_B_Sfield[6]==1'b1)
          I_I_DC_W_TriCrossRE=1'b1;
        else
          I_DC_W_Ssrc2re=1'b1;      
      end
    end
 
    6'b011011, //OR instruction
    6'b011010: //OR instruction
    begin
      I_DC_W_OR=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //MVC  src1(uint) src2(xuint)  dst(uint)          
        I_DC_W_Ssrc1re=1'b1;            
      //MVC  src1(scst5) src2(xuint)  dst(uint)          
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;            
    end

    6'b110011, //SHL instruction
    6'b110010, //SHL instruction
    6'b110000, //SHL instruction
    6'b110001, //SHL instruction
    6'b010011, //SHL instruction
    6'b010010: //SHL instruction
    begin
      I_DC_W_SHL=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //src1(uint)   
        I_DC_W_Ssrc1re=1'b1;
      else
        //src1(ucst)
        Src1_signed=1'b1;
      if(DP_B_Sfield[5]==1'b0)      
        //destination is long
        I_DC_W_U=1'b1;
      if(DP_B_Sfield[1]==1'b0)      
      begin
        //the source 2 is long data!
        I_DC_W_Ssrc2re=1'b1;
        I_I_DC_W_TriSTre=1'b1;
        I_DC_W_Src2_Type=1'b1;
      end
      else
      begin
        //the source 2 is reg data
        if(DP_B_Sfield[6]==1'b1)
          I_I_DC_W_TriCrossRE=1'b1;
        else
          I_DC_W_Ssrc2re=1'b1;
      end
    end

    6'b110111, //SHR instruction
    6'b110110, //SHR instruction
    6'b110101, //SHR instruction
    6'b110100, //SHR instruction
    6'b100111, //SHRU instruction
    6'b100110, //SHRU instruction
    6'b100101, //SHRU instruction
    6'b100100: //SHRU instruction
    begin
      I_DC_W_SHR=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //src1(uint)   
        I_DC_W_Ssrc1re=1'b1;
      else
        //src1(ucst)
        Src1_signed=1'b1;
      if(DP_B_Sfield[4]==1'b0)    
        //the operation is usigned SHRU
        I_DC_W_U=1'b1;  
      if(DP_B_Sfield[1]==1'b0)      
      begin
        //the source 2 is long data!
        I_DC_W_Ssrc2re=1'b1;
        I_I_DC_W_TriSTre=1'b1;
        I_DC_W_Src2_Type=1'b1;
      end
      else
      begin
        //the source 2 is reg data
        if(DP_B_Sfield[6]==1'b1)
          I_I_DC_W_TriCrossRE=1'b1;
        else
          I_DC_W_Ssrc2re=1'b1;
      end
    end
      
    6'b100011, //SSHL instruction
    6'b100010: //SSHL instruction
    begin
      I_DC_W_SSHL=1'b1;
      if(DP_B_Sfield[0]==1'b1)
        //src1(uint)   
        I_DC_W_Ssrc1re=1'b1;
      else
        //src1(ucst)
        Src1_signed=1'b1;
      if(DP_B_Sfield[6]==1'b1)
        I_I_DC_W_TriCrossRE=1'b1;
      else
        I_DC_W_Ssrc2re=1'b1;
    end

    6'b010111, //SUB instruction
    6'b010110: //SUB instruction
    begin
      I_DC_W_Src2inv=1'b1;