dc_s_decode.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module dc_s_decode (
                    DP_udst_Sfield,
                    clk,
                    reset,                                                         
                    stall,
                    DP_PCE1,
                    DP_W_Sactive,
                    DP_B_Sfield,
                    DP_B_Smode,
                    DP_W_SBDECBPOS,
                    DC_W_Src2_Type,
                    DC_W_Z,
                    DC_W_Condition_Exec,
                    
                    DC_W_U,                                    
                    DC_SUB2,
                    DC_SUB,
                    DC_SSHL,
                    DC_SHR,
                    DC_SHL,
                    DC_SET,
                    DC_BReg,
                    DC_OR,
                    DC_XOR,
                    DC_MVKH,
                    DC_MVC,
                    DC_EXT,
                    DC_MVK,
                    DC_CLR,
                    DC_BCst,
                    DC_AND,
                    DC_ADD2,
                    DC_ADD,
                    DC_SADD2,
                    DC_SADD,
                    DC_SADDU4,
                    DC_SADDUS2, 
                    DC_ADDKPC,				//c64
										DC_BDEC,
										DC_BPOS,
										DC_BNOP_Cst,
                    DC_CMPEQ2 , 
                    DC_CMPEQ4 , 
                    DC_CMPGT2 , 
                    DC_CMPGTU4 ,
                    DC_PACKH2,   
                    DC_PACKHL2,  
                    DC_PACKLH2,  
                    //DC_BNOP_Reg, 
                    DC_UNPKHU4,  
                    DC_UNPKLU4,  
                    DC_ANDN,     
                    DC_PACK2,    
                    DC_SHLMB,    
                    DC_SHRMB,    
                    DC_SPACK2,   
                    DC_SPACKU4,  
                    DC_SHR2,   
                    DC_SHRU2,	 				//end
                    DC_B_Src1,
                    DC_B_Dst_Address,                   
                    DC_W_Ssrc1re,
                    DC_B_Ssrc1addr,
                    DC_B_Src2,
                    DC_W_Ssrc2re,
                    DC_B_Ssrc2addr,
                    I_DC_W_TriSTre,
                    I_DC_B_TriSTaddr,
                    I_DC_W_TriCrossRE,                 
                    I_DC_B_TriCrossAddr,                 
                    DC_W_Scondre,                 
                    DC_B_Scondaddr,                 
                  //  I_DC_W_BCst,                 
		    					//	I_DC_W_BReg,                
                    DC_W_Sinvalid,                 
                    DC_W_S_SWBP,         // software bp decode add by liubw 2005-6-13
                    PDC_con_Value,        // real condition value  add by liubw 2005-6-13
                    Cst_BDEC ,  //add for BDEC & BPOS 
                    Ssrc1re,
                    Ssrc2re,
                    DC_W_TriCrossRE,
                    DC_W_TriSTre,
                    SSHL_SHL,
                    //SSHL_EXT,
                    SSHL_SHL_EXT,
                    SSHL_SHL_Src2Type, 
                    SHR_Src2Type_U,
                    SHR_SSHL,
                    SHR_Src2Type,
                    EXT_DC_U, 
                    log_reg,
                    use_result,
                    logic_use_result,
                    S_UBranch_Inst, // ADDKPC  BDEC  BNOP.Cst BNOP.Reg  BPOS  B cst  B reg            
                    DC_W_Src2inv,// the operand Src2  inv
                    SUB_RE
                   );

input [2:0]   DP_udst_Sfield;
input         clk;

input         reset;
      
input         stall;

input [31:0]  DP_PCE1;

input         DP_W_Sactive;
input[25:0]   DP_B_Sfield;
input[2:0]    DP_B_Smode;
input         DP_W_SBDECBPOS;
input [3:0]   PDC_con_Value;
output        DC_W_Src2_Type;
output        DC_W_Z;
output        DC_W_Condition_Exec;

output        DC_W_U;
output        DC_SUB2;
output        DC_SUB;
output        DC_SSHL;
output        DC_SHR;
output        DC_SHL;
output        DC_SET;
output        DC_BReg;
output        DC_OR;
output        DC_XOR;
output        DC_MVKH;
output        DC_MVC;
output        DC_EXT;
output        DC_MVK;
output        DC_CLR;
output        DC_BCst;
output        DC_AND;
output        DC_ADD2;
output        DC_ADD;
output        DC_SADD2;
output        DC_SADD;
output        DC_SADDU4;
output        DC_SADDUS2;

output 				DC_ADDKPC;
output 				DC_BDEC;
output 				DC_BPOS;
output 				DC_BNOP_Cst;
output 				DC_CMPEQ2;
output 				DC_CMPEQ4;
output 				DC_CMPGT2;
output 				DC_CMPGTU4;
output 				DC_PACKH2;
output 				DC_PACKHL2;
output 				DC_PACKLH2;
//output 				DC_BNOP_Reg;
output 				DC_UNPKHU4;
output 				DC_UNPKLU4;
output 				DC_ANDN;
output 				DC_PACK2;
output 				DC_SHLMB;
output 				DC_SHRMB;
output 				DC_SPACK2;
output 				DC_SPACKU4;
output 				DC_SHR2;
output 				DC_SHRU2;




output[31:0]  DC_B_Src1;
output[4:0]   DC_B_Dst_Address;
output        DC_W_Ssrc1re;
output[4:0]   DC_B_Ssrc1addr;
output[31:0]  DC_B_Src2;
output        DC_W_Ssrc2re;
output[4:0]   DC_B_Ssrc2addr;

output        I_DC_W_TriSTre;
output[4:0]   I_DC_B_TriSTaddr;
output        I_DC_W_TriCrossRE;
output[4:0]   I_DC_B_TriCrossAddr;
output        DC_W_Scondre;
output[2:0]   DC_B_Scondaddr;

output        DC_W_S_SWBP;
output[31:0]  Cst_BDEC;   //cst for BDEC & BPOS
output       SSHL_SHL;         
//output        SSHL_EXT;         
output        SSHL_SHL_EXT;     
output        SSHL_SHL_Src2Type; 
output        SHR_Src2Type_U;
output        SHR_SSHL;
output        SHR_Src2Type;
output        EXT_DC_U;
output        log_reg;
output        use_result;
output        logic_use_result;
////////////////////

output     Ssrc1re;
output     Ssrc2re;
output     DC_W_TriCrossRE;
output     DC_W_TriSTre;//input of S_unit

///////////////////////////////////Add output ports for INT/////////////////////////////////
//output		I_DC_W_BCst;
//output		I_DC_W_BReg;
output		DC_W_Sinvalid;

///////////////////////////////////END//////////////////////////////////////////////////////
output     S_UBranch_Inst;
output     DC_W_Src2inv;
output     SUB_RE;     // C64 new case  gongxiao




wire       S_UBranch_Inst;
reg        I_S_UBranch_Inst;

reg        DC_W_Src2_Type;
reg        DC_W_Z;
reg        DC_W_Condition_Exec;

reg        DC_W_U;
reg        DC_SUB2;
reg        DC_SUB;
reg        DC_SSHL;
reg        DC_SHR;
reg        DC_SHL;
reg        DC_SET;
reg        DC_BReg;
reg        DC_OR;
reg        DC_XOR;
reg        DC_MVKH;
reg        DC_MVC;
reg        DC_EXT;
reg        DC_MVK;
reg        DC_CLR;
reg        DC_BCst;
reg        DC_AND;
reg        DC_ADD2;
reg        DC_ADD;
reg        DC_SADD2;
reg        DC_SADD;
reg        DC_SADDU4;
reg        DC_SADDUS2;

reg				 DC_ADDKPC;   
reg				 DC_BDEC;     
reg				 DC_BPOS;     
reg				 DC_BNOP_Cst; 
reg				 DC_CMPEQ2;   
reg				 DC_CMPEQ4;   
reg				 DC_CMPGT2;   
reg				 DC_CMPGTU4;  
reg				 DC_PACKH2;   
reg				 DC_PACKHL2;  
reg				 DC_PACKLH2;  
//reg				 DC_BNOP_Reg; 
reg				 DC_UNPKHU4;  
reg				 DC_UNPKLU4;  
reg				 DC_ANDN;     
reg				 DC_PACK2;    
reg				 DC_SHLMB;    
reg				 DC_SHRMB;    
reg				 DC_SPACK2;   
reg				 DC_SPACKU4;  
reg				 DC_SHR2;       
reg				 DC_SHRU2;      


reg[31:0]  DC_B_Src1;
reg[4:0]   DC_B_Dst_Address;
wire       DC_W_Ssrc1re;
wire[4:0]  DC_B_Ssrc1addr;
reg[31:0]  DC_B_Src2;
wire       DC_W_Ssrc2re;
wire[4:0]  DC_B_Ssrc2addr;

wire       I_DC_W_TriSTre;
wire[4:0]  I_DC_B_TriSTaddr;
wire       I_DC_W_TriCrossRE;
wire[4:0]  I_DC_B_TriCrossAddr;
reg        DC_W_Scondre;
reg[2:0]   DC_B_Scondaddr;
wire [3:0] PDC_con_Value;
wire       DC_W_S_SWBP;

reg        I_DC_W_Src2_Type;
wire       I_DC_W_Z;
reg        I_DC_W_Condition_Exec;

reg        I_DC_W_U;
reg        I_DC_W_SUB2;
reg        I_DC_W_SUB;
reg        I_DC_W_SSHL;
reg        I_DC_W_SHR;
reg        I_DC_W_SHL;
reg        I_DC_W_SET;
reg        I_DC_W_BReg;
reg        I_DC_W_OR;
reg        I_DC_W_XOR;
reg        I_DC_W_MVKH;
reg        I_DC_W_MVC;
reg        I_DC_W_EXT;
reg        I_DC_W_MVK;
reg        I_DC_W_CLR;
reg        I_DC_W_BCst;
reg        I_DC_W_AND;
reg        I_DC_W_ADD2;
reg        I_DC_W_ADD;
reg        I_DC_W_SADD2;
reg        I_DC_W_SADD;
reg        I_DC_W_SADDU4;
reg        I_DC_W_SADDUS2;

reg        I_DC_W_ADDKPC;  
reg        I_DC_W_BDEC;    
reg        I_DC_W_BPOS;    
reg        I_DC_W_BNOP_Cst;
reg        I_DC_W_CMPEQ2;  
reg        I_DC_W_CMPEQ4;  
reg        I_DC_W_CMPGT2;  
reg        I_DC_W_CMPGTU4; 
reg        I_DC_W_PACKH2;  
reg        I_DC_W_PACKHL2; 
reg        I_DC_W_PACKLH2; 
//reg        I_DC_W_BNOP_Reg;
reg        I_DC_W_UNPKHU4; 
reg        I_DC_W_UNPKLU4; 
reg        I_DC_W_ANDN;    
reg        I_DC_W_PACK2;   
reg        I_DC_W_SHLMB;   
reg        I_DC_W_SHRMB;   
reg        I_DC_W_SPACK2;  
reg        I_DC_W_SPACKU4; 
reg        I_DC_W_SHR2;      
reg        I_DC_W_SHRU2;
reg        DC_W_TriSTre; 
reg        DC_W_TriCrossRE;
reg        Ssrc2re;
reg        Ssrc1re; 

wire        I_SSHL_SHL;         
//wire        I_SSHL_EXT;         
wire        I_SSHL_SHL_EXT;     
wire        I_SSHL_SHL_Src2Type;
reg        SSHL_SHL;         
//reg        SSHL_EXT;         
reg        SSHL_SHL_EXT;     
reg        SSHL_SHL_Src2Type;  
wire       I_SHR_Src2Type_U;
wire       I_SHR_SSHL;
wire       I_SHR_Src2Type;
wire       I_EXT_DC_U;
reg        SHR_Src2Type_U;
reg        SHR_SSHL;
reg        SHR_Src2Type;
reg        EXT_DC_U;
wire       I_log_reg;
reg        log_reg;
wire       I_use_result;
reg        use_result;
wire       I_logic_use_result;
reg        logic_use_result;

reg[31:0] I_DC_B_Src1; // hcm modified 2003-12-10.
wire[4:0]  I_DC_B_Dst_Address;
reg[31:0] I_DC_B_Src2;  //hcm modified 2003-12-10.

reg        I_I_DC_W_TriSTre;
reg        I_DC_W_Ssrc1re;
reg        I_DC_W_Ssrc2re;
reg        I_I_DC_W_TriCrossRE;
reg        I_DC_W_Scondre;
reg[2:0]   I_DC_B_Scondaddr;
wire        I_DC_W_Sinvalid;
reg        Src1_signed;

wire        Dst_use;
reg        I_SUB_RE; // case of  C64 add NEW

reg        Src1_ustab;

reg        PCE1_use;
reg [31:0]       Cst_BDEC;

wire[31:0]			 I_Cst_BDEC; 
reg        I_DC_W_Src2inv;
reg        DC_W_Src2inv;
reg        SUB_RE;
reg        DC_W_Sinvalid; 

assign   DC_W_S_SWBP = DP_W_Sactive & ((DP_B_Sfield[25:22] == 4'b0001)? 1'b1 : 1'b0);//调试时才为1，指令执行时为0
assign   I_DC_W_Z = (DC_W_S_SWBP == 1'b1)? PDC_con_Value[0]:DP_B_Sfield[22];


always @(posedge clk or negedge reset)
begin
  if(reset==1'b0)
  
  begin
    
    DC_W_Condition_Exec<=1'b0;
    DC_W_U<=1'b0;
    DC_SUB2<=1'b0;
    DC_SUB<=1'b0;
    DC_SSHL<=1'b0;
    DC_SHR<=1'b0;
    DC_SHL<=1'b0;
    DC_SET<=1'b0;
    DC_BReg<=1'b0;
    DC_OR<=1'b0;
    DC_XOR<=1'b0;
    DC_MVKH<=1'b0;
    DC_MVC<=1'b0;
    DC_EXT<=1'b0;
    DC_MVK<=1'b0;
    DC_CLR<=1'b0;
    DC_BCst<=1'b0;
    DC_AND<=1'b0;
    DC_ADD2<=1'b0;
    DC_ADD<=1'b0;            
    DC_SADD2<=1'b0;
    DC_SADD<=1'b0;
    DC_SADDU4<=1'b0;
    DC_SADDUS2<=1'b0;
    
    DC_ADDKPC<=1'b0;  
    DC_BDEC<=1'b0;    
    DC_BPOS<=1'b0;    
    DC_BNOP_Cst<=1'b0;
    DC_CMPEQ2<=1'b0;  
    DC_CMPEQ4<=1'b0;  
    DC_CMPGT2<=1'b0;  
    DC_CMPGTU4<=1'b0; 
    DC_PACKH2<=1'b0;  
    DC_PACKHL2<=1'b0; 
    DC_PACKLH2<=1'b0; 
    //DC_BNOP_Reg<=1'b0;
    DC_UNPKHU4<=1'b0; 
    DC_UNPKLU4<=1'b0; 
    DC_ANDN<=1'b0;    
    DC_PACK2<=1'b0;   
    DC_SHLMB<=1'b0;   
    DC_SHRMB<=1'b0;   
    DC_SPACK2<=1'b0;  
    DC_SPACKU4<=1'b0; 
    DC_SHR2<=1'b0;      
    DC_SHRU2<=1'b0;       
  
  
    
    DC_W_Scondre<=1'b0;
    DC_W_Scondre<=1'b0;
    DC_W_Z<=1'b0; 
    SSHL_SHL<=1'b0;         
    //SSHL_EXT<=1'b0;         
    SSHL_SHL_EXT<=1'b0;     
    SSHL_SHL_Src2Type<=1'b0;
    SHR_Src2Type_U<=1'b0;
    SHR_SSHL<=1'b0;
    SHR_Src2Type<=1'b0;
    EXT_DC_U<=1'b0;
    log_reg<=1'b0;
    use_result<=1'b0;
    logic_use_result<=1'b0;
    DC_W_Src2inv<=1'b0;
    SUB_RE<=1'b0;
    DC_W_Sinvalid<=1'b0;
    
    
  end
  else
  begin
    if(stall!=1'b1)

    begin
      
      DC_W_Condition_Exec<=I_DC_W_Condition_Exec;
      DC_W_U<=I_DC_W_U;
      DC_SUB2<=I_DC_W_SUB2;
      DC_SUB<=I_DC_W_SUB;
      DC_SSHL<=I_DC_W_SSHL;
      DC_SHR<=I_DC_W_SHR;
      DC_SHL<=I_DC_W_SHL;
      DC_SET<=I_DC_W_SET;
      DC_BReg<=I_DC_W_BReg;
      DC_OR<=I_DC_W_OR;
      DC_XOR<=I_DC_W_XOR;
      DC_MVKH<=I_DC_W_MVKH;
      DC_MVC<=I_DC_W_MVC;
      DC_EXT<=I_DC_W_EXT;
      DC_MVK<=I_DC_W_MVK;
      DC_CLR<=I_DC_W_CLR;
      DC_BCst<=I_DC_W_BCst;
      DC_AND<=I_DC_W_AND;
      DC_ADD2<=I_DC_W_ADD2;
      DC_ADD<=I_DC_W_ADD;
      DC_SADD2<=  I_DC_W_SADD2;
      DC_SADD<=  I_DC_W_SADD;
      DC_SADDU4<= I_DC_W_SADDU4;
      DC_SADDUS2<=I_DC_W_SADDUS2; 
      
      DC_ADDKPC<=I_DC_W_ADDKPC;   
      DC_BDEC<=I_DC_W_BDEC;     
      DC_BPOS<=I_DC_W_BPOS;     
      DC_BNOP_Cst<=I_DC_W_BNOP_Cst; 
      DC_CMPEQ2<=I_DC_W_CMPEQ2;   
      DC_CMPEQ4<=I_DC_W_CMPEQ4;   
      DC_CMPGT2<=I_DC_W_CMPGT2;   
      DC_CMPGTU4<=I_DC_W_CMPGTU4;  
      DC_PACKH2<=I_DC_W_PACKH2;   
      DC_PACKHL2<=I_DC_W_PACKHL2;  
      DC_PACKLH2<=I_DC_W_PACKLH2;  
      //DC_BNOP_Reg<=I_DC_W_BNOP_Reg; 
      DC_UNPKHU4<=I_DC_W_UNPKHU4;  
      DC_UNPKLU4<=I_DC_W_UNPKLU4;  
      DC_ANDN<=I_DC_W_ANDN;     
      DC_PACK2<=I_DC_W_PACK2;    
      DC_SHLMB<=I_DC_W_SHLMB;    
      DC_SHRMB<=I_DC_W_SHRMB;    
      DC_SPACK2<=I_DC_W_SPACK2;   
      DC_SPACKU4<=I_DC_W_SPACKU4;  
      DC_SHR2<=I_DC_W_SHR2;       
      DC_SHRU2<=I_DC_W_SHRU2;      
      DC_W_Scondre<=I_DC_W_Scondre;