s_syn.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps

module S_syn(
DC_B_Src1,
DC_Src2_Type, 					// when process fixed point operation, 1 stands for long or creg( BReg or MVC)
DC_B_Src2,
CtrlR_B_UData, 					// the data read from control register
DC_U, 									// denote the operation is unsigned or signed, 1 stands for unsigned
DC_Invalid,
en_instruction_execute,
DC_AND,
DC_BReg,
DC_MVC,
DC_MVK,
DC_MVKH,
DC_OR,
DC_XOR,
DC_PACKH2,    
DC_PACKHL2,   
DC_PACKLH2,   
//DC_BNOP_Reg,  
DC_UNPKHU4,   
DC_UNPKLU4,   
DC_ANDN,      
DC_PACK2,     
DC_SHLMB,     
DC_SHRMB,     
DC_SPACK2,    
DC_SPACKU4,   
DC_SHR2,      
DC_SHRU2,
syn_write_reg,
S_B_UWrite_Data, 						// the data need written  at E1 stage
S_URead_Creg, 							// when a creg value is a source operand, then S unit read the creg itself
logi_PCF,
S_UWrite_Creg, 							// the write control register signal of S unit at E1 stage
logi_branch,
S_SNMIE,
S_Interrupt_End,
logic_use_result
);

input         logic_use_result;
input         DC_AND;    
input         DC_BReg;
input         DC_MVC;
input         DC_MVK;
input         DC_MVKH;
input         DC_OR;
input         DC_XOR;
input	        DC_PACKH2;  
input         DC_PACKHL2; 
input         DC_PACKLH2; 
//input         DC_BNOP_Reg;
input         DC_UNPKHU4;
input         DC_UNPKLU4; 
input         DC_ANDN;    
input         DC_PACK2;   
input         DC_SHLMB;   
input         DC_SHRMB;   
input         DC_SPACK2;  
input         DC_SPACKU4; 
input         DC_SHR2;
input         DC_SHRU2;
input         DC_U;
input         en_instruction_execute;
input         DC_Invalid;
input [31:0]  DC_B_Src1;
input [31:0]  DC_B_Src2;
input	        DC_Src2_Type;
input [31:0]  CtrlR_B_UData;
output        syn_write_reg;
output[31:0]  S_B_UWrite_Data;
output[31:0]  logi_PCF;
output        S_URead_Creg;
output        S_UWrite_Creg;
output        logi_branch;
output        S_Interrupt_End;
output        S_SNMIE;
wire [31:0]   logi_output;
wire [31:0]   S_S_output;
wire          logi_write_reg;
wire          S_S_write_reg;
//wire [31:0]   Right_Shifter_16_Result;

S_logi s_logi  (
				        .DC_AND				(DC_AND), 
     		        .DC_BReg			(DC_BReg), 
   			        .DC_MVC				(DC_MVC), 
     		        .DC_MVK				(DC_MVK),
     		        .DC_MVKH			(DC_MVKH), 
     		        .DC_OR				(DC_OR ), 
     		        .DC_XOR				(DC_XOR), 
     		        .DC_W_PACKH2  	(DC_PACKH2  ),
     		        .DC_W_PACKHL2   (DC_PACKHL2 ),
     		        .DC_W_PACKLH2   (DC_PACKLH2 ),
     		        //.DC_W_BNOP_Reg  (DC_BNOP_Reg),
     		        .DC_W_UNPKHU4   (DC_UNPKHU4 ),
     		        .DC_W_UNPKLU4   (DC_UNPKLU4 ),
     		        .DC_W_ANDN      (DC_ANDN    ),
     		        .DC_W_PACK2     (DC_PACK2   ),
     		        .DC_W_SHLMB     (DC_SHLMB   ),
     		        .DC_W_SHRMB     (DC_SHRMB   ),
     		        .DC_W_SPACK2    (DC_SPACK2  ),
     		        .DC_W_SPACKU4   (DC_SPACKU4 ),
     		        .logi_PCF       (logi_PCF     ),
     		        .DC_Invalid			(DC_Invalid),
     		        .DC_B_Src1			(DC_B_Src1), 
   			        .DC_B_Src2			(DC_B_Src2),
   	  	        .CtrlR_B_UData			(CtrlR_B_UData ),
   	  	        .DC_Src2_Type		  	(DC_Src2_Type ), 
     		        .S_B_UWrite_Data		(logi_output ), 
     		        .en_instruction_execute		(en_instruction_execute),
     		        .logi_write_reg			(logi_write_reg ),
     		        .logi_branch			  (logi_branch ),
     		        .S_URead_Creg			  (S_URead_Creg ),
                .S_UWrite_Creg			(S_UWrite_Creg ),
                .S_SNMIE			      (S_SNMIE ),
			          .S_Interrupt_End  	(S_Interrupt_End ),
			          .logic_use_result   (logic_use_result)
								);

SHR2_SHRU2 SHR2_SHRU2 (
                .DC_B_Src2      (DC_B_Src2),
                .DC_B_Src1      (DC_B_Src1[4:0]),
                .DC_SHR2        (DC_SHR2),
                .DC_SHRU2       (DC_SHRU2),
                .DC_U           (DC_U),
                .SHR2_SHRU2_write_reg (S_S_write_reg),
                .S_B_UWrite_Data      (S_S_output),
                .en_instruction_execute (en_instruction_execute)
                //.Right_Shifter_16_Result(Right_Shifter_16_Result[31:0])
                );
                

assign syn_write_reg=logi_write_reg|S_S_write_reg;
assign S_B_UWrite_Data=(logi_write_reg|S_UWrite_Creg)?logi_output:S_S_output;

endmodule