s_unit.v

verilog, TMSC6415 S单元代码

// hds header_start
// hds header_end


`timescale 1ns/10ps

module S_Unit(
SUB_RE,
DC_W_Src2inv,
SSHL_SHL,
//SSHL_EXT,
SSHL_SHL_EXT,
SSHL_SHL_Src2Type,
SHR_Src2Type_U,
SHR_SSHL,
SHR_Src2Type,
EXT_DC_U,
log_reg,
use_result,
logic_use_result,
DC_Condition_Exec, 			// indicate the instruction is conditional execution
DC_Z, 									// indicate the z bit
CR_UZero, 							// come from register file, 1 when the conditional register is 0
DC_B_Src1,
DC_Src2_Type, 					// when process fixed point operation, 1 stands for long or creg( BReg or MVC)
Cst_BDEC,										//
PCF,										//
DC_B_Src2,
DC_B_Dst_Address,
CtrlR_B_UData, 					// the data read from control register
DC_W_U, 									// denote the operation is unsigned or signed, 1 stands for unsigned
I_DC_W_Sinvalid,
DC_ADD,
DC_ADD2,
DC_AND,
DC_BCst,
DC_BReg,
DC_CLR,
DC_EXT,
DC_MVC,
DC_MVK,
DC_MVKH,
DC_OR,
DC_SET,
DC_SHL,
DC_SHR,
DC_SSHL,
DC_SUB,
DC_SUB2,
DC_XOR,
DC_SADD2,
DC_SADD,
DC_SADDU4,
DC_SADDUS2,
DC_ADDKPC,		
DC_BDEC,      
DC_BPOS,      
DC_BNOP_Cst,  
DC_CMPEQ2 ,   
DC_CMPEQ4 ,   
DC_CMPGT2 ,   
DC_CMPGTU4 ,  
DC_PACKH2,    
DC_PACKHL2,   
DC_PACKLH2,   
//DC_BNOP_Reg,  
DC_UNPKHU4,   
DC_UNPKLU4,   
DC_ANDN,      
DC_PACK2,     
DC_SHLMB,     
DC_SHRMB,     
DC_SPACK2,    
DC_SPACKU4,   
DC_SHR2,      
DC_SHRU2,
RF_B_ST,
RF_B_S_src1,
RF_B_S_src2,
RF_B_CrossBarX,	 		
stall,
//clk,
//reset, 											// internal reset signal
S_B_UDst_Address, 					// the reg number need write to at E1 stage
S_B_UDst_Long_Address,
S_B_UWrite_Data, 						// the data need written  at E1 stage
S_B_UWrite_Long_Data,			  // the long data
S_UBranch, 									// indicate there is a branch taken
S_URead_Creg, 							// when a creg value is a source operand, then S unit read the creg itself
S_UCreg_Address,
S_UWrite_Creg, 							// the write control register signal of S unit at E1 stage
S_UWrite_Long_Reg,
S_UWrite_Reg, 							// the write register signal of S unit
S_SNMIE,
S_Interrupt_End,
S_W_SAT,
Ssrc1re,
Ssrc2re,
DC_W_TriCrossRE,
DC_W_TriSTre

);
// Internal Declarations

input         SUB_RE;
input         DC_W_Src2inv;
input         SSHL_SHL;
//input         SSHL_EXT;
input         SSHL_SHL_EXT;
input         SSHL_SHL_Src2Type;
input         SHR_Src2Type_U;
input         SHR_SSHL;
input         SHR_Src2Type;
input         EXT_DC_U ;
input         log_reg;
input         use_result;
input         logic_use_result;
input         CR_UZero;
input  [31:0] CtrlR_B_UData;
input         I_DC_W_Sinvalid;
input         DC_ADD;
input         DC_ADD2;
input         DC_AND;
input         DC_BCst;
input         DC_BReg;
input  [4:0]  DC_B_Dst_Address;
input  [7:0]  RF_B_ST;
input  [31:0] RF_B_S_src1;
input  [31:0] RF_B_S_src2;
input  [31:0] RF_B_CrossBarX;
input  [31:0] DC_B_Src1;
input  [31:0] DC_B_Src2;
input  [31:0]	Cst_BDEC;

input         DC_CLR;
input         DC_Condition_Exec;
input         DC_EXT;
input         DC_MVC;
input         DC_MVK;
input         DC_MVKH;
input         DC_OR;
input         DC_SET;
input         DC_SHL;
input         DC_SHR;
input         DC_SSHL;
input         DC_SUB;
input         DC_SUB2;
input         DC_XOR;
input         DC_SADD2;
input         DC_SADD;
input         DC_SADDU4;
input         DC_SADDUS2;

input 				DC_ADDKPC;    
input 				DC_BDEC;      
input 				DC_BPOS;      
input 				DC_BNOP_Cst;  
input 				DC_CMPEQ2;    
input 				DC_CMPEQ4;    
input 				DC_CMPGT2;    
input 				DC_CMPGTU4;   
input 				DC_PACKH2;    
input 				DC_PACKHL2;   
input 				DC_PACKLH2;   
//input 				DC_BNOP_Reg;  
input 				DC_UNPKHU4;   
input 				DC_UNPKLU4;   
input 				DC_ANDN;      
input 				DC_PACK2;     
input 				DC_SHLMB;     
input 				DC_SHRMB;     
input 				DC_SPACK2;    
input 				DC_SPACKU4;   
input 				DC_SHR2;      
input 				DC_SHRU2;     

input         DC_Src2_Type;
input         DC_W_U;
input         DC_Z;
input         stall;

//input         clk;
//input         reset;

input         Ssrc1re;
input         Ssrc2re;
input         DC_W_TriCrossRE;
input         DC_W_TriSTre;


output [4:0]  S_B_UDst_Address;
//output        S_Use_Long_Addr;
output [4:0]  S_B_UDst_Long_Address;

output [31:0] PCF;
output [31:0] S_B_UWrite_Data;
output [31:0] S_B_UWrite_Long_Data;
output        S_UBranch;
output        S_URead_Creg;
output [4:0]  S_UCreg_Address;
output        S_UWrite_Creg;
output        S_UWrite_Long_Reg;
output        S_UWrite_Reg;
output        S_SNMIE;
output        S_Interrupt_End;
output        S_W_SAT;


wire [31:0]   S_B_UWrite_Data;
wire          syn_write_reg;				//logi unit write reg
wire          math_write_reg;				//math unit write reg
wire          simd_write_reg;
wire          bit_write_reg;
wire          bit_write_long_reg;
wire          en_instruction_execute;
wire [31:0]   Syn_output;
wire [31:0]   math_output;
wire [31:0]   S_simdoutput;
wire [31:0]   bit_output;
wire [31:0]		math_PCF;
wire [31:0]		logi_PCF;
wire        I_S_UWrite_Creg;    		//hcm added 2004-5-10.为配合增加了调试断点
wire        I_S_UWrite_Long_Reg;    //hcm added 2004-5-10.为配合增加了调试断点
wire        I_S_UWrite_Reg;     		//hcm added 2004-5-10.为配合增加了调试断点
wire  [31:0] Src1;
wire  [31:0] Src2;
//reg     [31:0] Src2;
wire  [7:0]  DC_B_Src2_Long;
//wire         I_S_W_SAT;
wire         S_W_SAT_1;
wire         S_W_SAT_2;
//reg          S_W_SAT;
wire  [31:0]       Src2_1;
//wire  [31:0]       Src2_2;


S_Control S_Control(
                    .DC_Condition_Exec        (DC_Condition_Exec),
                    .DC_Z                     (DC_Z),
                    .CR_UZero                 (CR_UZero),
                    .DC_Invalid               (I_DC_W_Sinvalid),
                    .DC_Src2_Type             (DC_Src2_Type),
                    .DC_B_Dst_Address         (DC_B_Dst_Address),
                    .DC_B_Creg_Address        (DC_B_Src2[4:0]), //原代码为src2[4:0]，译码单元产生的读控制寄存器的地址
                    .syn_write_reg	          (syn_write_reg),
		     						.math_write_reg           (math_write_reg),
		     						.simd_write_reg          (simd_write_reg),
		 						    .bit_write_reg            (bit_write_reg),
		    					  .math_branch              (math_branch),
		    						.bit_write_long_reg       (bit_write_long_reg),
		    						.logi_branch              (logi_branch),
       					    .en_instruction_execute   (en_instruction_execute),
                    .S_B_UDst_Address         (S_B_UDst_Address), //写控制寄存器的地址也是此端口输入
                    .S_B_UDst_Long_Address    (S_B_UDst_Long_Address),
                    .S_UBranch                (S_UBranch),
                    .S_UCreg_Address          (S_UCreg_Address), //送到控制寄存器的地址
                    .S_UWrite_Long_Reg        (I_S_UWrite_Long_Reg),  //hcm added 2004-5-10.??????????
                    .S_UWrite_Reg             (I_S_UWrite_Reg)    //hcm added 2004-5-10.??????????
                    );

S_syn  S_syn  (
				            .DC_B_Src1                   (Src1              ),
                    .DC_Src2_Type 					     (DC_Src2_Type 					 ),
                    .DC_B_Src2                   (Src2              ),
                    .CtrlR_B_UData					     (CtrlR_B_UData 				 ),
                    .DC_U 									     (DC_W_U 									 ),
                    .DC_Invalid                  (I_DC_W_Sinvalid             ),
                    .en_instruction_execute      (en_instruction_execute ),
                    .DC_AND                      (DC_AND                 ),
                    .DC_BReg                     (DC_BReg                ),
                    .DC_MVC                      (DC_MVC                 ),
                    .DC_MVK                      (DC_MVK                 ),
                    .DC_MVKH                     (DC_MVKH                ),
                    .DC_OR                       (DC_OR                  ),
                    .DC_XOR                      (DC_XOR                 ),
                    .DC_PACKH2                   (DC_PACKH2              ),
                    .DC_PACKHL2                  (DC_PACKHL2             ),
                    .DC_PACKLH2                  (DC_PACKLH2             ),
                    //.DC_BNOP_Reg                 (DC_BNOP_Reg            ),
                    .DC_UNPKHU4                  (DC_UNPKHU4             ),
                    .DC_UNPKLU4                  (DC_UNPKLU4             ),
                    .DC_ANDN                     (DC_ANDN                ),
                    .DC_PACK2                    (DC_PACK2               ),
                    .DC_SHLMB                    (DC_SHLMB               ),
                    .DC_SHRMB                    (DC_SHRMB               ),
                    .DC_SPACK2                   (DC_SPACK2              ),
                    .DC_SPACKU4                  (DC_SPACKU4             ),
                    .DC_SHR2                     (DC_SHR2                ),
                    .DC_SHRU2                    (DC_SHRU2               ),
                    .syn_write_reg               (syn_write_reg          ),
                    .S_B_UWrite_Data 					   (Syn_output 			 ),
                    .S_URead_Creg 							 (S_URead_Creg 					 ),
                    .logi_PCF                    (logi_PCF               ),
                    .S_UWrite_Creg 						   (I_S_UWrite_Creg 				 ),
                    .logi_branch                 (logi_branch            ),
                    .S_SNMIE                     (S_SNMIE                ),
                    .S_Interrupt_End             (S_Interrupt_End        ),
                    .logic_use_result            (logic_use_result)
								);

S_math S_math  (
                .DC_B_Src1								(Src1 ),
								.DC_B_Src2								(Src2 ),
								.Cst_BDEC									(Cst_BDEC),
								.DC_ADD										(DC_ADD ),  
								.DC_BCst				          (DC_BCst ), 
								.DC_SUB		                (DC_SUB ),
								.DC_SADD                  (DC_SADD  ),  
								.DC_W_ADDKPC							(DC_ADDKPC	),
								.DC_W_BDEC			          (DC_BDEC		),
								.DC_W_BPOS				        (DC_BPOS		),
          			.DC_W_BNOP_Cst          	(DC_BNOP_Cst),
          			.S_B_UWrite_Data        	(math_output ), 
          			.math_PCF              		(math_PCF),
          			.en_instruction_execute 	(en_instruction_execute ),  
          			.math_write_reg           (math_write_reg ),
          			.math_branch              (math_branch ),	
          			.S_W_SAT				          (S_W_SAT_1 )
          			//.SUB_RE                   (SUB_RE)
          			
          			);


S_simd S_simd (
		              .DC_SADDU4                 (DC_SADDU4),
		              .DC_B_Src1                 (Src1             ),
							    .DC_B_Src2                 (Src2             ),
							    .DC_ADD2                   (DC_ADD2               ),
							    .DC_SUB2                   (DC_SUB2               ),
							    .DC_SADD2                (DC_SADD2            ),
							    .DC_SADDUS2              (DC_SADDUS2          ),
							    .DC_CMPEQ2               (DC_CMPEQ2           ),
							    .DC_CMPGT2               (DC_CMPGT2           ),
							    .DC_CMPEQ4             (DC_CMPEQ4),
							    .DC_CMPGTU4            (DC_CMPGTU4),
                  .DC_W_Src2inv              (DC_W_Src2inv          ),
							    .S_B_UWrite_Data          (S_simdoutput      ),
							    .en_instruction_execute    (en_instruction_execute),
							    .simd_write_reg		       (simd_write_reg		    )
               );

S_bit S_bit   (
	       			 .SSHL_SHL                        (SSHL_SHL),
               //.SSHL_EXT                        (SSHL_EXT),
               .SSHL_SHL_EXT                     (SSHL_SHL_EXT),
               .SSHL_SHL_Src2Type                (SSHL_SHL_Src2Type),
               .SHR_Src2Type_U                    (SHR_Src2Type_U),
               .SHR_SSHL                         (SHR_SSHL),
               .SHR_Src2Type                    (SHR_Src2Type),
               .EXT_DC_U                        (EXT_DC_U   ),
               .log_reg                         (log_reg),
               .use_result                      (use_result),
	       			 .S_W_SAT				(S_W_SAT_2 ), 
               .S_B_UWrite_Data			(bit_output ), 
               .S_B_UWrite_Long_Data		(S_B_UWrite_Long_Data ), 
               //.DC_Invalid			(I_DC_W_Sinvalid ),
               .DC_B_Src2_Long			(DC_B_Src2_Long ),
               .DC_CLR				(DC_CLR ), 
               .DC_EXT				(DC_EXT ), 
               .DC_SET				(DC_SET ), 
               .DC_SHL				(DC_SHL ), 
               .DC_SHR				(DC_SHR ), 
               .DC_SSHL				(DC_SSHL ), 
               //.DC_SHR2 			(DC_SHR2 ),
               //.DC_SHRU2      (DC_SHRU2),
               //.DC_Src2_Type			(DC_Src2_Type ),
               .en_instruction_execute		(en_instruction_execute ),
               .DC_U				(DC_W_U ), 
               .DC_B_Src1			(Src1[9:0] ), 
               .DC_B_Src2			(Src2), 
               //.S_Use_Long_Addr			(S_Use_Long_Addr ),
               .bit_write_reg			(bit_write_reg ),
               .bit_write_long_reg  		(bit_write_long_reg )
               );



assign S_B_UWrite_Data=simd_write_reg?S_simdoutput:(math_write_reg)?math_output:bit_write_reg?bit_output:Syn_output;
assign PCF=math_branch?math_PCF:logi_PCF;//发往DP
//assign 	I_S_W_SAT=S_W_SAT_1 || S_W_SAT_2;
assign   S_W_SAT=S_W_SAT_1 || S_W_SAT_2;

assign        S_UWrite_Creg = I_S_UWrite_Creg & (!stall);    //hcm added 2004-5-10.为配合增加了调试断点
assign        S_UWrite_Long_Reg = I_S_UWrite_Long_Reg & (!stall);    //hcm added 2004-5-10.为配合增加了调试断点
assign        S_UWrite_Reg = I_S_UWrite_Reg & (!stall);     //hcm added 2004-5-10.为配合增加了调试断点


/*assign        Src2_2[31:0]=(Ssrc2re)?RF_B_S_src2[31:0]:RF_B_CrossBarX;
assign        Src1[31:0]=(SUB_RE)?Src2_2[31:0]:(Ssrc1re)?RF_B_S_src1[31:0]:DC_B_Src1[31:0];
assign        Src2_1[31:0]=(SUB_RE)?RF_B_S_src1[31:0]:(Ssrc2re)?RF_B_S_src2[31:0]:(DC_W_TriCrossRE)?RF_B_CrossBarX:DC_B_Src2[31:0];
assign        Src2[31:0]=(DC_W_Src2inv)?(~Src2_1[31:0]):Src2_1[31:0];
assign        DC_B_Src2_Long[7:0]=DC_W_TriSTre?RF_B_ST[7:0]:8'hzz;*/
assign        Src1[31:0]=(SUB_RE)?(~RF_B_S_src1[31:0]):(Ssrc1re)?RF_B_S_src1[31:0]:DC_B_Src1[31:0];
assign        Src2_1[31:0]=(Ssrc2re)?RF_B_S_src2[31:0]:(DC_W_TriCrossRE)?RF_B_CrossBarX:DC_B_Src2[31:0];
assign        Src2[31:0]=(DC_W_Src2inv)?(~Src2_1[31:0]):Src2_1[31:0];
assign        DC_B_Src2_Long[7:0]=DC_W_TriSTre?RF_B_ST[7:0]:8'h00;//8'hzz




  
// 控制寄存器里已经把SAT锁存，不需在锁存
/*always @ (posedge clk or negedge reset) 
if (!reset) 
     S_W_SAT<=1'b0;
 else if (!stall)
     S_W_SAT<=I_S_W_SAT;*/
      
endmodule