mix.v

verilog, TMSC6415 S单元代码

module MIX(DC_MVK,DC_MVKH,DC_W_SHLMB,DC_W_SHRMB,MIX_out,DC_B_Src2,DC_B_Src1,DC_W_PACK2,DC_MVC);
      input [31:0] DC_B_Src2;
        input [31:0] DC_B_Src1;
        
      input   DC_MVK;
      input   DC_MVKH;
       input  DC_W_SHLMB;
      input  DC_W_SHRMB;
      input  DC_MVC;
      input  DC_W_PACK2;
       output [31:0]  MIX_out;
      reg  [31:0]   MIX_out;
always @( DC_MVK or DC_MVKH or DC_W_SHLMB or DC_W_SHRMB  or DC_B_Src2 or DC_B_Src1 or DC_W_PACK2 or DC_MVC)
       begin
            MIX_out=32'h0;
             if(DC_MVK)
                        MIX_out=DC_B_Src1;
              if(DC_MVKH)
                      MIX_out={DC_B_Src1[15:0],DC_B_Src2[15:0]};
             if(DC_W_SHLMB)
                    MIX_out={DC_B_Src2[23:16],DC_B_Src2[15:8],DC_B_Src2[7:0],DC_B_Src1[31:24]};
             if(DC_W_SHRMB)
                  MIX_out={DC_B_Src1[7:0],DC_B_Src2[31:24],DC_B_Src2[23:16],DC_B_Src2[15:8]};
             if(DC_MVC)
                  MIX_out=DC_B_Src2;
             if(DC_W_PACK2)
                  MIX_out={DC_B_Src1[15:0],DC_B_Src2[15:0]};
         end
endmodule