sshl.v

verilog, TMSC6415 S单元代码

`timescale 1ns/10ps
module sshl (Right_Shifter_Result,DC_B_Src2,en_instruction_execute,dst_SSHL,S_W_SAT,Left_Shifter_Result);

input  [31:0]  Right_Shifter_Result;//无符号右移移位的结果
input  [31:0]  DC_B_Src2;
//input  [9:0]  DC_B_Src1;
//input  [31:0]  src;
//input  [5:0]   count;
input  [31:0]  Left_Shifter_Result;
input          en_instruction_execute;
output [31:0]  dst_SSHL;
output         S_W_SAT;

reg    [31:0]  dst_SSHL;
reg            S_W_SAT;
//reg     [31:0]       result;
//reg            SAT_1;



/*always @(DC_B_Src2 or DC_B_Src1 or Left_Shifter_Result)
begin
   if(DC_B_Src1[5]) 
      begin
        if(DC_B_Src2[31]) 
           result=32'h80000000;
        else 
           result=32'h7fffffff;
        SAT_1=1;
      end
   else
      begin  
         result=Left_Shifter_Result[31:0];
         SAT_1=0;
      end 
end*/

always @(Right_Shifter_Result[31:1] or Left_Shifter_Result[31:0]  or en_instruction_execute or DC_B_Src2 )
begin
  if(({1'b1,~Right_Shifter_Result[31:1] }&DC_B_Src2)==32'h0||({1'b0,Right_Shifter_Result[31:1]}|DC_B_Src2)==32'hffffffff) 
     begin
    	 dst_SSHL=Left_Shifter_Result[31:0];
    	 S_W_SAT=0;//符号位不改变;
    end 
   
  else 
      begin
        if(DC_B_Src2[31]) dst_SSHL=32'h80000000;
          else dst_SSHL=32'h7fffffff;
            S_W_SAT=en_instruction_execute;
      end
end    
endmodule