s_logi.v

verilog, TMSC6415 S单元代码

`timescale 1ns / 1ns 

module S_logi (  
     		       DC_AND, 
     		       DC_BReg, 
   		         DC_MVC, 
     		       DC_MVK,
     		       DC_MVKH, 
     		       DC_OR, 
     		       DC_XOR, 
     		        DC_W_PACKH2,      
								DC_W_PACKHL2,      
								DC_W_PACKLH2, 
								//DC_W_BNOP_Reg,
								DC_W_UNPKHU4,                            
								DC_W_UNPKLU4,
								DC_W_ANDN,
								DC_W_PACK2,
								DC_W_SHLMB,
								DC_W_SHRMB,
								DC_W_SPACK2,
								DC_W_SPACKU4,
     		        logi_PCF,
     		       DC_Invalid,
     		       DC_B_Src1, 
   		         DC_B_Src2,
   		         CtrlR_B_UData,
   		         DC_Src2_Type, 
     		       S_B_UWrite_Data, 
     		       en_instruction_execute,
     		       logi_write_reg,
     		       logi_branch,
     		       S_URead_Creg,
               S_UWrite_Creg,
               S_SNMIE,
		           S_Interrupt_End,
		           logic_use_result
     		       );



input         logic_use_result;
input         DC_AND;    
input         DC_BReg;
input         DC_MVC;
input         DC_MVK;
input         DC_MVKH;
input         DC_OR;
input         DC_XOR;
input	        DC_W_PACKH2;  
input         DC_W_PACKHL2; 
input         DC_W_PACKLH2; 
//input         DC_W_BNOP_Reg;
input         DC_W_UNPKHU4;
input         DC_W_UNPKLU4; 
input         DC_W_ANDN;    
input         DC_W_PACK2;   
input         DC_W_SHLMB;   
input         DC_W_SHRMB;   
input         DC_W_SPACK2;  
input         DC_W_SPACKU4; 
input         en_instruction_execute;
input         DC_Invalid;
input [31:0]  DC_B_Src1;
input [31:0]  DC_B_Src2;
input	        DC_Src2_Type;
input [31:0]  CtrlR_B_UData;
output [31:0] S_B_UWrite_Data;
output [31:0] logi_PCF;
output        logi_write_reg;
output	      logi_branch;
output        S_URead_Creg;
output        S_UWrite_Creg;
output        S_SNMIE;
output        S_Interrupt_End;

  
wire [31:0]    pcf;
wire [31:0]    dst_low_32;
wire          use_result;
wire [31:0]    dst_low_32_1;
wire [31:0]    dst_low_32_2;
wire [31:0]    dst_low_32_3;
wire [31:0]    dst_low_32_4;


/*assign use_result=(DC_AND||DC_MVK||DC_MVKH||DC_OR||DC_XOR||DC_W_PACKH2||      
								DC_W_PACKHL2 ||      
								DC_W_PACKLH2 || 
								//DC_W_BNOP_Reg ||
								DC_W_UNPKHU4 ||                            
								DC_W_UNPKLU4 ||
								DC_W_ANDN ||
								DC_W_PACK2 ||
								DC_W_SHLMB ||
								DC_W_SHRMB ||
								DC_W_SPACK2 ||
								DC_W_SPACKU4);*/ //译码站
assign logi_write_reg=(logic_use_result||DC_MVC&&DC_Src2_Type)&&en_instruction_execute;
assign logi_branch=en_instruction_execute&&DC_BReg;
assign S_URead_Creg=DC_Invalid&&DC_Src2_Type&&(DC_MVC||DC_BReg);

wire   S_URead_Creg_1;
assign S_URead_Creg_1=DC_Invalid&&DC_Src2_Type&&(DC_BReg);
assign logi_PCF=S_URead_Creg_1?CtrlR_B_UData:pcf;

assign S_UWrite_Creg=en_instruction_execute&&DC_MVC&&!DC_Src2_Type;
assign S_SNMIE=en_instruction_execute&&DC_BReg&&DC_Src2_Type&&DC_B_Src2[0];  //NRP 00111
assign S_Interrupt_End=en_instruction_execute&&DC_BReg&&DC_Src2_Type&&!DC_B_Src2[0];  //IRP 00110

//assign  pcf=DC_B_Src2&{32{DC_BReg||DC_W_BNOP_Reg}}; 
assign  pcf=DC_B_Src2&{32{DC_BReg}};
assign  dst_low_32=dst_low_32_1 | dst_low_32_2 | dst_low_32_3 | dst_low_32_4;
assign S_B_UWrite_Data=S_URead_Creg?CtrlR_B_UData:dst_low_32;



S_UPACK   S_UPACK(
                   .DC_B_Src1(DC_B_Src1),
                   .DC_B_Src2(DC_B_Src2),
                   .DC_W_PACKH2(DC_W_PACKH2),
                   .DC_W_PACKHL2(DC_W_PACKHL2),
                   .DC_W_PACKLH2(DC_W_PACKLH2),
                   .DC_W_UNPKHU4(DC_W_UNPKHU4),
                   .DC_W_UNPKLU4(DC_W_UNPKLU4),
                   .S_UPACK_out(dst_low_32_1[31:0])
                                      )  ;// 无符号打包解包指令


MIX      MIX(
             .DC_W_PACK2(DC_W_PACK2),
             .DC_MVC(DC_MVC),
             .DC_MVK(DC_MVK),
             .DC_MVKH(DC_MVKH),
             .DC_W_SHLMB(DC_W_SHLMB),
             .DC_W_SHRMB(DC_W_SHRMB),
             .MIX_out(dst_low_32_2[31:0]),
             .DC_B_Src2(DC_B_Src2),
             .DC_B_Src1(DC_B_Src1)
        );                              // 线赋值、拼接指令


logical  logical(.DC_XOR(DC_XOR),
                 .DC_AND(DC_AND),
                 .DC_OR(DC_OR),
                 .DC_ANDN(DC_W_ANDN),
                 .DC_B_Src1(DC_B_Src1),
                 .DC_B_Src2(DC_B_Src2),
                 .logical_out(dst_low_32_3[31:0])
                                     ); // 普通逻辑指令


S_PACK    S_PACK(
                  .DC_W_SPACK2(DC_W_SPACK2),
                  .DC_W_SPACKU4(DC_W_SPACKU4),
                  .DC_B_Src2(DC_B_Src2),
                  .DC_B_Src1(DC_B_Src1),
                  .S_PACK_out(dst_low_32_4[31:0])
                      );               //  有符号打包指令



endmodule